Patents by Inventor Yu-Chi Wang

Yu-Chi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11562972
    Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 24, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Yu-Chi Shen, Tzyy-Jang Tseng, Chen-Hua Cheng, Pei-Wei Wang
  • Patent number: 11563088
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 24, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20230014825
    Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure, a second type semiconductor structure, an active structure and a contact structure. The first type semiconductor structure is located on the substrate and has a first protrusion part with a first thickness and a platform part with a second thickness. The second type semiconductor structure is located on the first type semiconductor structure. The active structure is between the first type semiconductor structure and the second type semiconductor structure. The contact structure is disposed between the first type semiconductor structure and the substrate. The second thickness of the platform part is in a range of 0.01 ?m to 1 ?m.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 19, 2023
    Inventors: Chung-Hao WANG, Yu-Chi WANG, Yi-Ming CHEN, Yi-Yang CHIU, Chun-Yu LIN
  • Patent number: 11532550
    Abstract: The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11527609
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh Su, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin
  • Publication number: 20220388293
    Abstract: A method for preparing a bifunctional film, including: (a) drying a first polymer solution to form a film to form an anti-adhesion layer, and (b) drying a second polymer solution over the anti-adhesion layer to form a film to form an attachment layer. The first polymer solution includes a first hydrophobic solution and a first hydrophilic solution, and in the first polymer solution, the weight ratio of the solute of the first hydrophobic solution to the solute of the first hydrophilic solution is 1:0.01-1. Moreover, the second polymer solution is composed of a second hydrophilic solution.
    Type: Application
    Filed: August 11, 2022
    Publication date: December 8, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Hsin SHEN, Yu-Chi WANG, Ming-Chia YANG, Yu-Bing LIOU, Wei-Hong CHANG, Yun-Han LIN, Hsin-Yi HSU, Yun-Chung TENG, Chia-Jung LU, Yi-Hsuan LEE, Jian-Wei LIN, Kun-Mao KUO, Ching-Mei CHEN
  • Publication number: 20220378971
    Abstract: This invention provides an air disinfecting device for disinfecting or decontaminate air, which comprises a first metal plate and a second metal plate opposite to the first metal plate, a UVC LED mounted on the first metal plate, and a power supply providing power to the UVC LED. The second metal plate has an area large enough such that lights emitted from the UVC LED will be enclosed inside the air disinfection device.
    Type: Application
    Filed: September 7, 2021
    Publication date: December 1, 2022
    Inventors: Bor-Jen WU, Chia-Bin TSEN, Yu-Yen WANG, Hui-Chi HSU, Hsien-Hsin TSAI
  • Publication number: 20220384333
    Abstract: A device includes a sensor die having a sensing region at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front-side redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front-side redistribution structure exposes the sensing region of the sensor die, and wherein the front-side redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization pattern on the first dielectric layer, and a second dielectric layer extending over the metallization pattern and the first dielectric layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: December 1, 2022
    Inventors: Yung-Chi Chu, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20220378973
    Abstract: This invention provides an air disinfecting device for disinfecting or decontaminate air, which comprises a first metal plate and a second metal plate opposite to the first metal plate, a UVC LED mounted on the first metal plate, and a power supply providing power to the UVC LED. The second metal plate has an area large enough such that lights emitted from the UVC LED will be enclosed inside the air disinfection device.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Inventors: Bor-Jen WU, Chia-Bin TSEN, Yu-Yen WANG, Hui-Chi HSU, Hsien-Hsin TSAI
  • Patent number: 11508818
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: November 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11504802
    Abstract: A multifunctional laser processing apparatus includes a hollow milling shaft, a light path tool holder, a tool-holder-type melting module, a laser light source, and a temperature sensor. The hollow milling shaft includes a first light path channel and a connection portion. The light path tool holder can be connected to the connection portion. The light path tool holder has a second light path channel communicating with the first light path channel. The tool-holder-type melting module can be connected to the connection portion. The tool-holder-type melting module has a third light path channel communicating with the first light path channel. The laser light source is configured to emit a laser light beam toward the first light path channel. The temperature sensor is disposed on an outer surface of the hollow milling shaft and is configured to sense a temperature of a work piece during a multifunctional processing process.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: November 22, 2022
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Yu-Ting Lyu, Hsiang-Pin Wang, Po-Chi Hu, Chao-Yung Yeh
  • Publication number: 20220367284
    Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain electrodes; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside, wherein the two metal plugs and the isolation structure form sidewalls of a trench; and a dielectric liner on the sidewalls of the trench, wherein the dielectric liner partially or fully surrounds an air gap within the trench.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220367663
    Abstract: The present disclosure provides a semiconductor device structure that includes: a fin active region extruded above a semiconductor substrate; a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and a conductive feature electrically connected to the gate electrode or the S/D features. The conductive feature includes a bottom metal feature of a first metal; a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; a barrier layer surrounding both the top metal feature and the bottom metal feature; and a liner surrounding both the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin
  • Publication number: 20220359388
    Abstract: The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Chun-Yuan Chen, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220359649
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Huan-Chieh Su, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin
  • Patent number: 11495491
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive structure and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a second conductive structure partially surrounded by the second dielectric layer and partially surrounded by the first conductive structure. In addition, the semiconductor device structure includes an interfacial layer separating the first conductive structure from the second conductive structure.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11477187
    Abstract: In an approach for an API key access authorization, a processor receives a transaction identity, a part of a token, and an API key identity attribute from a server. The transaction identity is generated in the server associated with generating the token. A processor receives a request from a client with the transaction identity for the part of the token. A processor looks up a transaction table via the transaction identity as an index. The transaction identity is associated with the part of the token and the API key identity attribute. A processor retrieves a client identity attribute through a second server via an IP address of the client. The second server registers the client. A processor matches a policy via the API key identity attribute and the client identity attribute. A processor sends the part of the token to the client.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Yi Fei He, Gang Tang, Hua Hong Wang, Xiaoli Xu, Yu Chi Li
  • Publication number: 20220320292
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Application
    Filed: February 28, 2022
    Publication date: October 6, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11458715
    Abstract: A method for preparing a bifunctional film, including: (a) drying a first polymer solution to form a film to form an anti-adhesion layer; and (b) drying a second polymer solution over the anti-adhesion layer to form a film to form an attachment layer. The first polymer solution includes a first hydrophobic solution and a first hydrophilic solution, and in the first polymer solution, the weight ratio of the solute of the first hydrophobic solution to the solute of the first hydrophilic solution is 1:0.01-1. Moreover, the second polymer solution consists of a second hydrophilic solution.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: October 4, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin Shen, Yu-Chi Wang, Ming-Chia Yang, Yu-Bing Liou, Wei-Hong Chang, Yun-Han Lin, Hsin-Yi Hsu, Yun-Chung Teng, Chia-Jung Lu, Yi-Hsuan Lee, Jian-Wei Lin, Kun-Mao Kuo, Ching-Mei Chen
  • Publication number: 20220310794
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 29, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang