Patents by Inventor Yu-Chiang Liao
Yu-Chiang Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11636902Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.Type: GrantFiled: September 8, 2021Date of Patent: April 25, 2023Assignee: PHISON ELECTRONICS CORP.Inventors: Guan-Wei Wu, Jen-Chu Wu, Jen-Huo Wang, Yu-Chiang Liao, Shih-Yang Sun
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Publication number: 20230048903Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.Type: ApplicationFiled: September 8, 2021Publication date: February 16, 2023Applicant: PHISON ELECTRONICS CORP.Inventors: Guan-Wei Wu, Jen-Chu Wu, Jen-Huo Wang, Yu-Chiang Liao, Shih-Yang Sun
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Patent number: 11101003Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.Type: GrantFiled: March 2, 2020Date of Patent: August 24, 2021Assignee: PHISON ELECTRONICS CORP.Inventors: Jen-Chu Wu, Bo-Jing Lin, Yu-Chiang Liao
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Publication number: 20210257033Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.Type: ApplicationFiled: March 2, 2020Publication date: August 19, 2021Applicant: PHISON ELECTRONICS CORP.Inventors: Jen-Chu Wu, Bo-Jing Lin, Yu-Chiang Liao
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Patent number: 11075637Abstract: A signal generation circuit is disclosed according to an embodiment of the invention. The signal generation circuit includes a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is configured to generate a phase control signal according to a phase adjustment signal. The bias control circuit is configured to generate a bias voltage according to the phase control signal. The phase interpolation circuit is configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used to adjust a current of the phase interpolation circuit to correct an error of the clock signal.Type: GrantFiled: December 3, 2019Date of Patent: July 27, 2021Assignee: PHISON ELECTRONICS CORP.Inventors: Jen-Chu Wu, Yu-Chiang Liao
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Publication number: 20210143822Abstract: A signal generation circuit is disclosed according to an embodiment of the invention. The signal generation circuit includes a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is configured to generate a phase control signal according to a phase adjustment signal. The bias control circuit is configured to generate a bias voltage according to the phase control signal. The phase interpolation circuit is configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used to adjust a current of the phase interpolation circuit to correct an error of the clock signal.Type: ApplicationFiled: December 3, 2019Publication date: May 13, 2021Applicant: PHISON ELECTRONICS CORP.Inventors: Jen-Chu Wu, Yu-Chiang Liao
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Patent number: 10749728Abstract: A signal calibration circuit including a first phase interpolator, a second phase interpolator, a phase detector, a control circuit and a delay circuit is provided according to an exemplary embodiment of the disclosure. The first phase interpolator is configured to receive a plurality of first signals and generate a plurality of first quadrature signals according to the first signals. The second phase interpolator is configured to generate a second signal according to the first quadrature signals. The phase detector is configured to detect a phase difference between the second signal and one of the first signals. The control circuit is configured to generate a calibration parameter according to the phase difference. The delay circuit is configured to adjust at least one of the first signals according to the calibration parameter, such that the adjusted first signal includes a plurality of second quadrature signals.Type: GrantFiled: March 25, 2019Date of Patent: August 18, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Jen-Chu Wu, Yu-Chiang Liao
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Publication number: 20200252258Abstract: A signal calibration circuit including a first phase interpolator, a second phase interpolator, a phase detector, a control circuit and a delay circuit is provided according to an exemplary embodiment of the disclosure. The first phase interpolator is configured to receive a plurality of first signals and generate a plurality of first quadrature signals according to the first signals. The second phase interpolator is configured to generate a second signal according to the first quadrature signals. The phase detector is configured to detect a phase difference between the second signal and one of the first signals. The control circuit is configured to generate a calibration parameter according to the phase difference. The delay circuit is configured to adjust at least one of the first signals according to the calibration parameter, such that the adjusted first signal includes a plurality of second quadrature signals.Type: ApplicationFiled: March 25, 2019Publication date: August 6, 2020Applicant: PHISON ELECTRONICS CORP.Inventors: Jen-Chu Wu, Yu-Chiang Liao
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Patent number: 9716506Abstract: A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.Type: GrantFiled: September 10, 2016Date of Patent: July 25, 2017Assignee: PHISON ELECTRONICS CORP.Inventors: Wei-Yung Chen, Yu-Chiang Liao
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Patent number: 9712175Abstract: A clock and data recovery circuit module and a phase lock method are provided. The module includes a phase detection circuit, a converter circuit and a voltage control oscillation circuit. The phase detection circuit is configured to detect a phase difference between a data signal and a feedback clock. The converter circuit is coupled to the phase detection circuit and configured to output a first phase control voltage and a second phase control voltage according to the phase difference. The voltage control oscillation circuit is coupled to the converter circuit and configured to receive the first phase control voltage and the second phase control voltage and output the feedback clock according to the first phase control voltage and the second phase control voltage.Type: GrantFiled: September 10, 2016Date of Patent: July 18, 2017Assignee: PHISON ELECTRONICS CORP.Inventors: Wei-Yung Chen, Yu-Chiang Liao
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Publication number: 20170019116Abstract: A clock and data recovery circuit module and a phase lock method are provided. The module includes a phase detection circuit, a converter circuit and a voltage control oscillation circuit. The phase detection circuit is configured to detect a phase difference between a data signal and a feedback clock. The converter circuit is coupled to the phase detection circuit and configured to output a first phase control voltage and a second phase control voltage according to the phase difference. The voltage control oscillation circuit is coupled to the converter circuit and configured to receive the first phase control voltage and the second phase control voltage and output the feedback clock according to the first phase control voltage and the second phase control voltage.Type: ApplicationFiled: September 10, 2016Publication date: January 19, 2017Applicant: PHISON ELECTRONICS CORP.Inventors: Wei-Yung Chen, Yu-Chiang Liao
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Publication number: 20160380639Abstract: A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.Type: ApplicationFiled: September 10, 2016Publication date: December 29, 2016Applicant: PHISON ELECTRONICS CORP.Inventors: Wei-Yung Chen, Yu-Chiang Liao
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Patent number: 9479183Abstract: A memory storage device having a clock and data recovery circuit module are provided. The module includes sampling circuits, a first logic circuit module, a delay circuit module, a second logic circuit module, a frequency adjustment circuit and a clock control circuit. The sampling circuits sample a data signal according to reference clocks. The first logic circuit module performs a first logic operation according to a sampling result. The delay circuit module delays a result of the first logic operation. The second logic circuit module performs a second logic operation according to said result and the delayed first logic result. The frequency adjustment circuit outputs a frequency adjustment signal according to a result of the second logic operation, and the clock control circuit performs a phase locking accordingly. Therefore, a circuit complexity of the clock and data recovery circuit module may be reduced.Type: GrantFiled: June 22, 2015Date of Patent: October 25, 2016Assignee: PHISON ELECTRONICS CORP.Inventors: Wei-Yung Chen, Yu-Chiang Liao
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Publication number: 20160308539Abstract: A clock and data recovery circuit module, a memory storage device and a phase lock method are provided. The module includes sampling circuits, a first logic circuit module, a delay circuit module, a second logic circuit module, a frequency adjustment circuit and a clock control circuit. The sampling circuits sample a data signal according to reference clocks. The first logic circuit module performs a first logic operation according to a sampling result. The delay circuit module delays a result of the first logic operation. The second logic circuit module performs a second logic operation according to said result and the delayed first logic result. The frequency adjustment circuit outputs a frequency adjustment signal according to a result of the second logic operation, and the clock control circuit performs a phase locking accordingly. Therefore, a circuit complexity of the clock and data recovery circuit module may be reduced.Type: ApplicationFiled: June 22, 2015Publication date: October 20, 2016Inventors: Wei-Yung Chen, Yu-Chiang Liao