Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: A liquid storage tank includes a housing, a piston located in the housing, a cover, an elastic element, and an outlet pipe. The cover is attached to the housing and has a support post extending toward the piston. The piston, the housing, and the cover define a tank chamber. The tank chamber is filled with cooling liquid. The elastic element is connected with the tank hosing and the piston. The elastic element is free from contact with the cooling liquid. The outlet pipe communicates with the tank chamber. An extension direction of an opening of the outlet pipe is not parallel to a direction of movement of the elastic element. When the cooling liquid is decreased, the piston compressed the tank chamber such that the elastic element is released. The tank chamber is continuously compressed by pairing the elastic element and the piston.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: A method includes: forming a bottom electrode over a substrate; depositing a first seed layer over the bottom electrode, the first seed layer having an amorphous crystal phase; performing a first surface treatment on the first seed layer, wherein after the first surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom electrode adjacent to the first seed layer; depositing an upper layer over the dielectric layer; and performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A novel quantum dot capable of near infrared emissions at wavelengths of 750-1100 is made by forming solid solutions of metal sulfide, metal selenide or metal sulfide selenide by incorporating a suitable amount of an additional metallic element or elements to provide an emission wavelength in the range of 750 nm to 1100 nm. The quantum dots may be enabled for bioconjugation and may be used in a method for tissue imaging and analyte detection.

Abstract: The present invention relates to a continuous reactor a method for manufacturing nanoparticles. The reactor of the present invention includes: a plurality of first inputs for individually inputting a plurality of reagents; a first mixing part connected to the first inputs to mix the reagents; N number of first reaction units, each comprising a plurality of first diverging channels and a first converging channel to form a channel having the first diverging channels and the first converging channels alternately connected to one another in series for N times of diverging-converging actions, wherein N?1, and the first diverging channels of a 1st one of the first reaction units are connected to the first mixing part; and a first output connected to the first converging channel of an Nth one of the first reaction units, so as to output a product of nanoparticles.

Abstract: A novel quantum dot capable of near infrared emissions at wavelengths of 750-1100 is made by forming solid solutions of metal sulfide, metal selenide or metal sulfide selenide by incorporating a suitable amount of an additional metallic element or elements to provide an emission wavelength in the range of 750 nm to 1100 nm. The quantum dots may be enabled for bioconjugation and may be used in a method for tissue imaging and analyte detection.

Abstract: A novel quantum dot capable of near infrared emissions at wavelengths of 750-1100 is made by forming solid solutions of metal sulfide, metal selenide or metal sulfide selenide by incorporating a suitable amount of an additional metallic element or elements to provide an emission wavelength in the range of 750 nm to 1100 nm. The quantum dots may be enabled for bioconjugation and may be used in a method for tissue imaging and analyte detection.

Abstract: The present invention relates to a continuous reactor a method for manufacturing nanoparticles. The reactor of the present invention includes: a plurality of first inputs for individually inputting a plurality of reagents; a first mixing part connected to the first inputs to mix the reagents; N number of first reaction units, each comprising a plurality of first diverging channels and a first converging channel to form a channel having the first diverging channels and the first converging channels alternately connected to one another in series for N times of diverging-converging actions, wherein N?1, and the first diverging channels of a 1st one of the first reaction units are connected to the first mixing part; and a first output connected to the first converging channel of an Nth one of the first reaction units, so as to output a product of nanoparticles.

Abstract: A novel quantum dot capable of near infrared emissions at wavelengths of 750-1100 is made by forming solid solutions of metal sulfide, metal selenide or metal sulfide selenide by incorporating a suitable amount of an additional metallic element or elements to provide an emission wavelength in the range of 750 nm to 1100 nm. The quantum dots may be enabled for bioconjugation and may be used in a method for tissue imaging and analyte detection.

Abstract: The present invention relates to a high-concentration nanoscale silver colloidal solution and the preparing process thereof. The colloidal solution of the present invention comprises a high content of silver particles, i.e. approximately 1.5 wt %. The mean size of the nanoscale silver is less than 10 nm. In the preparing process, silver salt, ionic chelating agent, stabilizing agent, reducing agent, solvent and reaction accelerator are homogeneously mixed together. The increase of reaction temperature by external heat source accelerates completed reaction. By using the specified reaction accelerator and chelating agent and under the operating condition of the present invention, high-density silver colloidal solution is obtained while inhibiting particle aggregation. Therefore, the resulting nanoscale silver colloidal solution contains very small-sized particles and the stability thereof is satisfactory.