Patents by Inventor YU-CHIEH LU

YU-CHIEH LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12167607
    Abstract: A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Georgios Vellianitis, Marcus Johannes Henricus Van Dal, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 12159870
    Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Shu Huang, Jhih-Bin Chen, Ming Chyi Liu, Yu-Chang Jong, Chien-Chih Chou, Jhu-Min Song, Yi-Kai Ciou, Tsung-Chieh Tsai, Yu-Lun Lu
  • Publication number: 20240397725
    Abstract: A field-effect transistor (FET), selectively switchable between first and second states, includes: source and drain regions and a channel region disposed therebetween; a gate arranged to selectively receive a bias voltage which switches the FET between the first and second states; a memory structure between the gate and the channel region, structure including a first portion which is anti-ferroelectric and a second portion which is ferroelectric, both portions being polarized in a first direction when the FET is in the first state; and a depolarization dielectric layer disposed proximate to the memory structure. When the FET is set to the first state, the depolarization dielectric layer destabilizes a polarization of the second portion of the memory structure while maintaining a polarization of the first portion.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 28, 2024
    Inventors: Chun-Chieh Lu, Yu-Ming Lin, Kuo-Chang Chiang, Yu-Chuan Shih, Huai-Ying Huang
  • Publication number: 20240396214
    Abstract: This document describes methods and systems for an antenna system integrated with side-keys of an electronic device. The antenna system enables antenna integration in a metal frame using a metal support structure and fastener(s) to route antenna signals around side-key modules embedded in the frame without encountering or causing interference with the side-key modules. By using these techniques to integrate antennas on areas around the side-key modules, more antennas can be implemented on the electronic device, leading to improved capabilities supporting additional wireless standards and a better user experience in terms of improved communication quality.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: Google LLC
    Inventors: Jeng-Hau Lu, Yu-Chieh Lin, Min-Sen Kuo, Chia-Chi Huang, Ying-Chih Wang
  • Publication number: 20240387383
    Abstract: An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and a dielectric foam disposed between the first and second portions of the conductive layer. The dielectric foam includes fluid gaps filled with carbon dioxide gas.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Yu-Teng DAI, Chih-Wei LU, Hsin-Chieh YAO, Chung-Ju LEE
  • Publication number: 20240377436
    Abstract: A tunnel-type probe includes a tube, an elastic member, and a pin. The elastic member is assembled in the tube. The pin is movably disposed through the tube, and is electrically coupled to the tube by being connected to the elastic member. The pin has an inner segment, a contacting segment, and a limiting segment, the latter two of which are connected to two ends of the inner segment. The inner segment is arranged in the tube and is connected to the elastic member. The contacting segment and the limiting segment are respectively located at two opposite sides of the tube. When the tunnel probe abuts against a device under test (DUT) through the contacting segment, the pin is moved in a direction away from the DUT, such that the elastic member is deformed from being pressed by the pin so as to generate an elastic force.
    Type: Application
    Filed: April 11, 2024
    Publication date: November 14, 2024
    Inventors: YU-JU LU, YI-HSIEN CHEN, MENG-CHIEH CHENG, WEI-JHIH SU
  • Publication number: 20240377437
    Abstract: An open-type probe of a vertical probe card includes a frame, an elastic member, and a pin. The frame has an operation slot and two lateral openings being in spatial communication with the operation slot. The elastic member is assembled to the frame and is located in the operation slot. The pin includes an inner segment assembled in the operation slot and a contacting segment that protrudes from an opening of the operation slot. The pin abuts against the elastic member through the inner segment so as to be electrically coupled to the frame. The elastic member and the inner segment are arranged between the two lateral openings. The contacting segment is configured to abut against a device under test, so that the contacting segment is moved toward the operation slot to press the elastic member for deforming the elastic member to generate an elastic force.
    Type: Application
    Filed: April 11, 2024
    Publication date: November 14, 2024
    Inventors: YU-JU LU, YI-HSIEN CHEN, MENG-CHIEH CHENG, WEI-JHIH SU
  • Publication number: 20240381654
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a multi-layer stack disposed on a substrate and having a plurality of conductive layers interleaved between a plurality of dielectric layers. A channel layer is arranged along a side of the multi-layer stack. A ferroelectric material is arranged between the channel layer and the side of the multi-layer stack. A plurality of oxygen scavenging layers are respectively arranged between the ferroelectric material and sidewalls of the plurality of conductive layers. The plurality of oxygen scavenger layers are entirely confined below the plurality of dielectric layers.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
  • Publication number: 20240371770
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate, a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect conductive structure arranged within the second interconnect dielectric layer. The interconnect conductive structure includes an outer portion that has a first conductive material. Further, the interconnect conductive structure includes a central portion having outermost sidewalls surrounded by the outer portion of the interconnect conductive structure. The central portion includes a second conductive material different than the first conductive material.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Yu-Teng Dai, Hsi-Wen Tien, Wei-Hao Liao, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20240371779
    Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Yen Huang, Chia-Tien Wu
  • Publication number: 20240365553
    Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 31, 2024
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chi On Chui, Han-Jong Chia, Chenchen Jacob Wang
  • Publication number: 20240363716
    Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Wu-Wei TSAI, Chun-Chieh LU, Hai-Ching CHEN, Yu-Ming LIN, Sai-Hooi YEONG
  • Publication number: 20240365461
    Abstract: The present disclosure is directed to a modularized vessel droplet generator assembly (MGDVA) including a droplet generator assembly (DGA). Under a normal operation, the liquid fuel moves along an operation pathway extending through the DGA to eject or discharge the liquid fuel (e.g., liquid tin) from a nozzle of the DGA into a vacuum chamber. The liquid fuel in the vacuum chamber is then exposed to a laser generating an extreme ultra-violet (EUV) light. Under a service operation, the operation pathway is closed and a service pathway extending through the DGA is opened. A gas is introduced into the service pathway forming a gas-liquid interface between the gas and the liquid fuel. The gas-liquid interface is driven to an isolation valve directly adjacent to the DGA. In other words, the gas pushes back the liquid fuel to the isolation valve. Once the gas-liquid interface reaches the isolation valve, the isolation valve is closed isolating the DGA from the liquid fuel.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Kuang SUN, Ming-Hsun TSAI, Wei-Shin CHENG, Cheng-Hao LAI, Hsin-Feng CHEN, Chiao-Hua CHENG, Cheng-Hsuan WU, Yu-Fa LO, Jou-Hsuan LU, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20240365460
    Abstract: The present disclosure is directed to a modularized vessel droplet generator assembly (MGDVA) including a droplet generator assembly (DGA). Under a normal operation, the liquid fuel moves along an operation pathway extending through the DGA to eject or discharge the liquid fuel (e.g., liquid tin) from a nozzle of the DGA into a vacuum chamber. The liquid fuel in the vacuum chamber is then exposed to a laser generating an extreme ultra-violet (EUV) light. Under a service operation, the operation pathway is closed and a service pathway extending through the DGA is opened. A gas is introduced into the service pathway forming a gas-liquid interface between the gas and the liquid fuel. The gas-liquid interface is driven to an isolation valve directly adjacent to the DGA. In other words, the gas pushes back the liquid fuel to the isolation valve. Once the gas-liquid interface reaches the isolation valve, the isolation valve is closed isolating the DGA from the liquid fuel.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Kuang SUN, Ming-Hsun TSAI, Wei-Shin CHENG, Cheng-Hao LAI, Hsin-Feng CHEN, Chiao-Hua CHENG, Cheng-Hsuan WU, Yu-Fa LO, Jou-Hsuan LU, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Patent number: 12125795
    Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Yen Huang, Chia-Tien Wu
  • Publication number: 20240347377
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Patent number: 12113115
    Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wu-Wei Tsai, Chun-Chieh Lu, Hai-Ching Chen, Yu-Ming Lin, Sai-Hooi Yeong
  • Publication number: 20240324235
    Abstract: Provided is a ferroelectric memory device having a dielectric layer vertically interleaved between a first conductive line and a second conductive line. A first ferroelectric portion is arranged along a sidewall of the first conductive line and a second ferroelectric portion is arranged along a sidewall of the second conductive line. A channel layer is arranged along sides of the dielectric layer, the first conductive line, and the second conductive line. A topmost surface of the first ferroelectric portion is vertically separated from a bottommost surface of the second ferroelectric portion by the channel layer.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Inventors: Chun-Chieh Lu, Han-Jong Chia, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin
  • Publication number: 20240321626
    Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.
    Type: Application
    Filed: May 29, 2024
    Publication date: September 26, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yang Du, Yung-Fong Lin, Tsung-Hsiang Lin, Yu-Chieh Chou, Cheng-Tao Chou, Yi-Chun Lu, Chun-Hsu Chen
  • Patent number: 12101939
    Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chi On Chui, Han-Jong Chia, Chenchen Jacob Wang