Patents by Inventor Yu-Chieh Su

Yu-Chieh Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11756839
    Abstract: A method for manufacturing a MOS transistor includes following. A gate stack structure and a hardmask layer on the gate stack structure are sequentially formed on a substrate. A first spacer is formed on sidewalls of the gate stack structure and the hardmask layer. A photoresist layer is formed on a sidewall of the first spacer. A top surface of the photoresist layer is higher than a top surface of the gate stack structure. The hardmask layer and a portion of the first spacer are removed to expose the top surface of the gate stack structure. A top surface of a remaining first spacer is higher than the top surface of the gate stack structure. The photoresist layer is removed. A second spacer is formed on a sidewall of the remaining first spacer. A top surface of the second spacer is higher than the top surface of the gate stack.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: September 12, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wan-Yan Lin, Yu-Chieh Su, Ming-Chien Chiu, Mao-Hsing Chiu
  • Publication number: 20220216113
    Abstract: A method for manufacturing a MOS transistor includes following. A gate stack structure and a hardmask layer on the gate stack structure are sequentially formed on a substrate. A first spacer is formed on sidewalls of the gate stack structure and the hardmask layer. A photoresist layer is formed on a sidewall of the first spacer. A top surface of the photoresist layer is higher than a top surface of the gate stack structure. The hardmask layer and a portion of the first spacer are removed to expose the top surface of the gate stack structure. A top surface of a remaining first spacer is higher than the top surface of the gate stack structure. The photoresist layer is removed. A second spacer is formed on a sidewall of the remaining first spacer. A top surface of the second spacer is higher than the top surface of the gate stack.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 7, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wan-Yan Lin, Yu-Chieh Su, Ming-Chien Chiu, Mao-Hsing Chiu
  • Publication number: 20170277935
    Abstract: A fingerprint enrollment method and a fingerprint enrollment apparatus are provided. A minutiae feature and a pore feature of a first fingerprint image are extracted to obtain a first template. A minutiae feature and a pore feature of a second fingerprint image are extracted to obtain a second template. A minutiae matching score between the minutiae features of the first template and the minutiae features of the second template is calculated. When the minutiae matching score is between the first threshold and a second threshold, stitching, mosaicking or synthesis of the first template and the second template are performed by utilizing a matching relation between the pore features of the first template and the pore features of the second template and utilizing the matching relation between the minutiae feature of the first template and the minutiae feature of the second template.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 28, 2017
    Inventors: Jau-Hong Kao, Yu-Chieh Su, Yi-Jen Wu
  • Patent number: 9773147
    Abstract: A fingerprint enrollment method and a fingerprint enrollment apparatus are provided. A minutiae feature and a pore feature of a first fingerprint image are extracted to obtain a first template. A minutiae feature and a pore feature of a second fingerprint image are extracted to obtain a second template. A minutiae matching score between the minutiae features of the first template and the minutiae features of the second template is calculated. When the minutiae matching score is between the first threshold and a second threshold, stitching, mosaicking or synthesis of the first template and the second template are performed by utilizing a matching relation between the pore features of the first template and the pore features of the second template and utilizing the matching relation between the minutiae feature of the first template and the minutiae feature of the second template.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: September 26, 2017
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jau-Hong Kao, Yu-Chieh Su, Yi-Jen Wu