Abstract: A robotic fish includes a front body, a rear body that includes a first segment and a second segment, and a driving unit. The first segment has a front engaging portion projecting toward and pivotally connected to the front body, and a rear engaging portion formed with a recess that recedes toward the front body and pivotally connected to the second segment. The driving unit includes a motor disposed in the front engaging portion, and a shaft extending along a dorsoventral axis and connecting the motor and the rear connecting portion. A ratio of a distance between the shaft and a foremost edge of the front engaging portion to a distance between the foremost edge and an extreme point of the recess ranges from 0.075 to 0.75.

Abstract: A robotic fish includes a front body, a rear body that includes a first segment and a second segment, and a driving unit. The first segment has a front engaging portion projecting toward and pivotally connected to the front body, and a rear engaging portion formed with a recess that recedes toward the front body and pivotally connected to the second segment. The driving unit includes a motor disposed in the front engaging portion, and a shaft extending along a dorsoventral axis and connecting the motor and the rear connecting portion. A ratio of a distance between the shaft and a foremost edge of the front engaging portion to a distance between the foremost edge and an extreme point of the recess ranges from 0.075 to 0.75.

Abstract: A method of creating an augmented reality (AR) environment is implemented using an AR device and includes: controlling an image capturing unit to capture images of a movable electronic in a real environment; transmitting the action command to the movable electronic device to enable the movable electronic device to move; generating an AR image based on the images of the movable electronic device, the AR image including the movable electronic device located at a calculated location in the AR image, the calculated location being calculated based on a current location of the movable electronic device in the real environment; and displaying the AR image so as to present an AR environment.

Abstract: The invention provides a three-dimensional (3D) image processing circuit and a synchronization signal correction method thereof. The 3D image processing circuit is adapted to process a 3D image signal. The 3D image signal includes an image synchronization signal and a view switching signal. The 3D image processing circuit includes a synchronization signal correction circuit coupled to the image processing circuit. A synchronization circuit of the synchronization signal correction circuit receives an image synchronization signal processed by the image processing circuit and simultaneously receives the view switching signal. The synchronization circuit compares the processed image synchronization signal with the view switching signal, so as to output a view switching signal synchronized with the processed image synchronization signal. The invention further provides an image display device including the above 3D image processing circuit.

Abstract: A boot method for a platform system including a Universal Extensible Firmware Interface (UEFI) Basic Input/Output System (BIOS) is provided. The UEFI BIOS includes partitions storing an initial boot program code, a factory setting boot program code, a first customized boot program code, a second customized boot program code and boot information respectively. The provided method comprises steps of: loading the initial boot program code stored in one of the partitions of the UEFI BIOS into a memory, and executing the initial boot program code stored in the memory by a CPU to perform a first phase of boot; and loading one of the factory setting boot program code, the first customized boot program code and the second customized boot program code stored in the partitions of the UEFI BIOS into the memory according to data in the boot information, and executing the program code loaded in the memory to perform a second phase of boot by the CPU.

Abstract: A boot method for a platform system including a Universal Extensible Firmware Interface (UEFI) Basic Input/Output System (BIOS) is provided. The UEFI BIOS includes partitions storing an initial boot program code, a factory setting boot program code, a first customized boot program code, a second customized boot program code and boot information respectively. The provided method comprises steps of: loading the initial boot program code stored in one of the partitions of the UEFI BIOS into a memory, and executing the initial boot program code stored in the memory by a CPU to perform a first phase of boot; and loading one of the factory setting boot program code, the first customized boot program code and the second customized boot program code stored in the partitions of the UEFI BIOS into the memory according to data in the boot information, and executing the program code loaded in the memory to perform a second phase of boot by the CPU.

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract: A semiconductor package, an array arranged substrate structure for the semiconductor package, and fabrication method of the semiconductor package are disclosed. First, a substrate having a plurality of array arranged substrate units is provided, and electroplating buses are formed between the substrate units. Each substrate unit has a plurality of electrically connecting pads and a plurality of conductive traces for connecting the electrically connecting pads to the electroplating buses such that an electroplating metallic layer can be formed on the electrically connecting pads via the electroplating buses and the conductive traces. Then, slots are further formed between the substrate units for disconnecting connections between the conductive traces and the electroplating buses, thus, enable each of the substrate units to become electrically independent from each other for a pre-proceeding electrical O/S test.

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.