Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking 10 structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: An integrated chip including a gate layer. An insulator layer is over the gate layer. A channel structure is over the insulator layer. A pair of source/drains are over the channel structure and laterally spaced apart by a dielectric layer. The channel structure includes a first channel layer between the insulator layer and the pair of source/drains, a second channel layer between the insulator layer and the dielectric layer, and a third channel layer between the second channel layer and the dielectric layer. The first channel layer, the second channel layer, and the third channel layer include different semiconductors.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a first oxide material having a first sidewall and a second sidewall, a first spacer layer in contact with the first sidewall of the first oxide material, the first spacer layer having a first conductivity type, a second spacer layer in contact with the second sidewall of the first oxide material, wherein the second spacer layer has the first conductivity type. The memory device also includes a channel layer having a second conductivity type that is opposite to the first conductivity type, wherein the channel layer is in contact with the first oxide material, the first spacer layer, and the second spacer layer. The memory device further includes a ferroelectric layer in contact with the channel layer.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a gate, a ferroelectric layer disposed on the gate; a first channel layer disposed on the ferroelectric layer, a second channel layer disposed on the ferroelectric layer, and source and drain regions disposed on the first channel layer. The first channel layer includes a first thickness and the second channel layer includes a second thickness. A ratio of the first thickness and the second thickness is less than 3/5.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.

Abstract: A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.

Abstract: A dynamic random access memory (DRAM) and a manufacturing method thereof are disclosed. A storage cell of the DRAM includes a FINFET and a capacitor. A gate of the FINFET is formed by a metal nitride or a carbonized metal having the effect of stress-induced strain. A gate dielectric of the FINFET and/or a dielectric of the capacitor can be formed by a ferroelectric material having negative capacitance characteristics. A strained-gate engineering is used in the invention achieve effects of (1) increasing ferro-electricity of the dielectric to enhance the operation speed and endurance of the FINFET; and (2) enhancing the ferro negative capacitance effect to improve the sub-threshold swing of the FINFET, so that the switching power and the off-current of the FINFET can be reduced and the charge retention capability of capacitor can be effectively enhanced to improve the operation characteristics of the DRAM.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a source and a drain, a p-type nitride layer and a strain gate. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source and the drain are respectively disposed at two sides of the barrier layer. The p-type nitride layer is disposed on the barrier layer. The strain gate is disposed over the p-type nitride layer for tuning a first strain of the channel layer and a second strain of the barrier layer.

Abstract: A three-dimensional non-volatile memory structure including a substrate, a stacked structure, a charge storage pillar, a channel pillar, and a ferroelectric material pillar is provided. The stacked structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked. The charge storage pillar is disposed in the stacked structure. The channel pillar is disposed inside the charge storage pillar. The ferroelectric material pillar is disposed inside the channel pillar.

Abstract: The invention provides a semiconductor device including a substrate, a first dielectric layer, a conductive layer, a ferroelectric material layer, and a charge-trapping layer. The first dielectric layer is disposed on the substrate. The conductive layer is disposed on the first dielectric layer. The ferroelectric material layer and the charge-trapping layer are disposed between the first dielectric layer and the conductive layer by stacking. The semiconductor device of the invention has better memory characteristics and transistor characteristics.