Patents by Inventor Yu-Chien Lin

Yu-Chien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11570063
    Abstract: A Quality of Experience (QoE) optimization system and method are provided. An electronic device inputs key performance indicators (KPIs) and system control parameters collected from a core network, a base station and a user equipment (UE) into a QoE optimization model. The QoE optimization model then optimizes the system control parameters based on the KPIs and a user QoE fed back from the UE to output optimized system control parameters. Furthermore, a strategy emulator controls at least one of a base station emulator and a UE emulator, so as to emulate the QoE optimization model using the at least one of the base station emulator and the UE emulator. Non-real-time optimization adjustments to the QoE optimization model are made based on the result of the emulation performed by the at least one of the base station emulator and the UE emulator.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: January 31, 2023
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Ta-Sung Lee, En-Cheng Liou, Yu-Chien Lin, Ting-Yen Kuo, Ching-Hsiang Lin
  • Patent number: 11564908
    Abstract: Provided is a long-acting method for preventing or treating glucose metabolism disorders that includes administering a beta-lactam compound or a pharmaceutically acceptable salt thereof to a subject in need thereof. The method for preventing or treating glucose metabolism disorders has a long-acting effect that lasts more than two days even after medication has been stopped.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: January 31, 2023
    Assignee: GLYCOLYSIS BIOMED CO., LTD.
    Inventors: Feng-Ling Lee, Lung-Jr Lin, Jyh-Shing Hsu, Cheng-Hsien Hsu, Yen-Chun Huang, Ya-Chien Huang, Chun-Tsung Lo, Hui-Fang Liao, Yu-Wen Liu, Yu-Chi Kao
  • Publication number: 20220406815
    Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: YU-CHIEN CHIU, MENG-HAN LIN, CHUN-FU CHENG, HAN-JONG CHIA, CHUNG-WEI WU, ZHIQIANG WU
  • Publication number: 20220367559
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-Zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-Kai Tsao, Yung-Lung Yang
  • Patent number: 11502123
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-kai Tsao, Yung-Lung Yang
  • Publication number: 20220359606
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S.S. Wang
  • Patent number: 11458478
    Abstract: An integrated stage for holding rapid test reagent cards includes two U-shaped sidewalls opposite to each other, a first receiving space, a second receiving space, and an elastic sheet. The U-shaped sidewalls cooperatively define the first receiving space. The second receiving space is formed in the first receiving space and is lower than the first receiving space. The elastic sheet is arranged on a short side of the first receiving space. The first receiving space is used for allowing the integrated stage to hold a first rapid test reagent card. The second receiving space is used for allowing the integrated stage to hold a second rapid test reagent card. The integrated stage utilizes the elastic sheet to hold and fix the first rapid test reagent card or the second rapid test reagent card.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: October 4, 2022
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yu-Cheng Lin, Wei-Chien Weng, Kai-Wen Lin
  • Publication number: 20220286369
    Abstract: A Quality of Experience (QoE) optimization system and method are provided. An electronic device inputs key performance indicators (KPIs) and system control parameters collected from a core network, a base station and a user equipment (UE) into a QoE optimization model. The QoE optimization model then optimizes the system control parameters based on the KPIs and a user QoE fed back from the UE to output optimized system control parameters. Furthermore, a strategy emulator controls at least one of a base station emulator and a UE emulator, so as to emulate the QoE optimization model using the at least one of the base station emulator and the UE emulator. Non-real-time optimization adjustments to the QoE optimization model are made based on the result of the emulation performed by the at least one of the base station emulator and the UE emulator.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 8, 2022
    Inventors: Ta-Sung Lee, En-Cheng Liou, Yu-Chien Lin, Ting-Yen Kuo, Ching-Hsiang Lin
  • Patent number: 11419852
    Abstract: Provided is a long-acting method for preventing or treating glucose metabolism disorders that includes administering a beta-lactam compound or a pharmaceutically acceptable salt thereof to a subject in need thereof. The method for preventing or treating glucose metabolism disorders has a long-acting effect that lasts more than two days even after medication has been stopped.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 23, 2022
    Assignee: GLYCOLYSIS BIOMED CO., LTD.
    Inventors: Feng-Ling Lee, Lung-Jr Lin, Jyh-Shing Hsu, Cheng-Hsien Hsu, Yen-Chun Huang, Ya-Chien Huang, Chun-Tsung Lo, Hui-Fang Liao, Yu-Wen Liu, Yu-Chi Kao
  • Publication number: 20220216113
    Abstract: A method for manufacturing a MOS transistor includes following. A gate stack structure and a hardmask layer on the gate stack structure are sequentially formed on a substrate. A first spacer is formed on sidewalls of the gate stack structure and the hardmask layer. A photoresist layer is formed on a sidewall of the first spacer. A top surface of the photoresist layer is higher than a top surface of the gate stack structure. The hardmask layer and a portion of the first spacer are removed to expose the top surface of the gate stack structure. A top surface of a remaining first spacer is higher than the top surface of the gate stack structure. The photoresist layer is removed. A second spacer is formed on a sidewall of the remaining first spacer. A top surface of the second spacer is higher than the top surface of the gate stack.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 7, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wan-Yan Lin, Yu-Chieh Su, Ming-Chien Chiu, Mao-Hsing Chiu
  • Patent number: 11360206
    Abstract: The present invention provides a detection device and a method with simplified computing manner A transmitter transmits detection signals to an environment to detect a target. At least a portion of the detection signals are reflected by the target to generate a plurality of reflection signals. A receiver comprises a plurality of receiving units. Each of the receiving units receives the reflection signals to generate a receiving signal. A processing module connected to the receiver includes a conversion unit, an integration unit and a computing unit. The conversion unit converts the receiving signals into transformation signals by a time-domain to frequency-domain transformation. The integration unit integrates the transformation signals into a first integration signal and a second integration signal. The computing unit decomposes the first integration signal and the second integration signal to 1D arrays.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: June 14, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ta-Sung Lee, Kuan-Hen Lin, Yu-Chien Lin, Yun-Han Pan
  • Patent number: 11309980
    Abstract: A system for synthesizing signal of user equipment and a method thereof are provided. The system includes a physical channel modeler and a physical channel training module. The physical channel modeler receives geo information of a field under test of and a sparse real physical field channel feature to build a physical channel model. The physical channel modeler estimates a plurality of predefined positions of the geo information to obtain a plurality of simulated physical field channel features corresponding to the predefined positions. The physical channel training module receives and performs training on the geo information, the sparse real physical field channel feature and the simulated physical field channel features by using an AI algorithm to perform an inference of a fully real physical field channel feature.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 19, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: En Cheng Liou, Ta-Sung Lee, Chia-Hung Lin, Yu-Chien Lin
  • Patent number: 11282495
    Abstract: A first neural network model of a user device processes audio data to extract audio embeddings that represent vocal characteristics of a user of an utterance represented in the audio data. The audio embeddings may then be hashed to remove characteristics specific to the user while still maintaining a unique set of characteristics. The hashed embeddings may be sent to a remote system, which may use them to identify the user.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 22, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Hongda Mao, George Yu-Chien Lin, Sundararajan Srinivasan, Chu-Cheng Hsieh
  • Patent number: 11269052
    Abstract: A signal processing method is provided. First, at least one transmitted signal is output to at least one target, and the target reflects at least one reflected signal to receiving antennas, which then generate receiving signals upon receipt of the reflected signal. Next, the transmitted signal and each receiving signal are processed to generate processing signals. The processing signals are arranged in a form of matrix, to generate a channel coefficient matrix having M×N channel coefficient matrix blocks. Next, the channel coefficient matrix is divided into Ndivide×Mdivide secondary channel coefficient matrices, which are then substituted into a snapshot vector matrix equation to generate a snapshot vector matrix for calculating an angle of the target. The signal processing method can establish an optimal secondary channel coefficient matrix arrangement by using a special signal preprocessing manner, to improve the resolution and accuracy of the estimated angle parameter of the target.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 8, 2022
    Assignee: National Chiao Tung University
    Inventors: Ta-Sung Lee, Yu-Chien Lin, Yun-Han Pan
  • Publication number: 20220066919
    Abstract: An AI decision based multiple telecommunication endpoints system is provided, including a telecommunication endpoint device and an artificial intelligence decision controller. The telecommunication endpoint device performs a communication test with the radio frequency communication device under test. The artificial intelligence decision controller is electrically connected to the telecommunication terminal device to control the communication test, and performs an efficiency analysis on the result of the communication test, and generates a decision instruction according to the result of the efficiency analysis.
    Type: Application
    Filed: August 4, 2021
    Publication date: March 3, 2022
    Inventors: En-Cheng Liou, Ta-Sung Lee, Kai-Ten Feng, Yu-Chien Lin, Chia-Hung Lin
  • Publication number: 20210399816
    Abstract: A system for synthesizing signal of user equipment and a method thereof are provided. The system includes a physical channel modeler and a physical channel training module. The physical channel modeler receives geo information of a field under test of and a sparse real physical field channel feature to build a physical channel model. The physical channel modeler estimates a plurality of predefined positions of the geo information to obtain a plurality of simulated physical field channel features corresponding to the predefined positions. The physical channel training module receives and performs training on the geo information, the sparse real physical field channel feature and the simulated physical field channel features by using an AI algorithm to perform an inference of a fully real physical field channel feature.
    Type: Application
    Filed: September 22, 2020
    Publication date: December 23, 2021
    Applicant: National Chiao Tung University
    Inventors: En Cheng Liou, Ta-Sung Lee, Chia-Hung Lin, Yu-Chien LIN
  • Patent number: 11196220
    Abstract: An electrical connector includes an insulating body having a mating slot, which has a first inner wall and a second inner wall facing each other vertically. A ground terminal is fixed to the insulating body, and has a first contact portion exposed on a higher surface of the first inner wall. A grounding member has a second contact portion and a third contact portion both exposed on a lower surface of the first inner wall. The second contact portion is located closer to the second inner wall relative to the higher surface. In a vertical direction, the third contact portion is located farther away from the second inner wall relative to the higher surface. The second contact portion is grounded and conductively connected to the first electrical component inside the mating slot to form a first ground loop. The first contact portion is conductively connected to the first ground loop.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: December 7, 2021
    Assignee: LINTES TECHNOLOGY CO., LTD
    Inventors: Jin Yi Tu, Shih Chi Kuan, Yu Chien Lin
  • Publication number: 20210183358
    Abstract: A first neural network model of a user device processes audio data to extract audio embeddings that represent vocal characteristics of a user of an utterance represented in the audio data. The audio embeddings may then be hashed to remove characteristics specific to the user while still maintaining a unique set of characteristics. The hashed embeddings may be sent to a remote system, which may use them to identify the user.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 17, 2021
    Inventors: Hongda Mao, George Yu-Chien Lin, Sundararajan Srinivasan, Chu-Cheng Hsieh
  • Publication number: 20210165090
    Abstract: The present invention provides a detection device and a method with simplified computing manner A transmitter transmits detection signals to an environment to detect a target. At least a portion of the detection signals are reflected by the target to generate a plurality of reflection signals. A receiver comprises a plurality of receiving units. Each of the receiving units receives the reflection signals to generate a receiving signal. A processing module connected to the receiver includes a conversion unit, an integration unit and a computing unit. The conversion unit converts the receiving signals into transformation signals by a time-domain to frequency-domain transformation. The integration unit integrates the transformation signals into a first integration signal and a second integration signal. The computing unit decomposes the first integration signal and the second integration signal to 1D arrays.
    Type: Application
    Filed: July 7, 2020
    Publication date: June 3, 2021
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: TA-SUNG LEE, KUAN-HEN LIN, YU-CHIEN LIN, YUN-HAN PAN
  • Publication number: 20210021087
    Abstract: An electrical connector includes an insulating body having a mating slot, which has a first inner wall and a second inner wall facing each other vertically. A ground terminal is fixed to the insulating body, and has a first contact portion exposed on a higher surface of the first inner wall. A grounding member has a second contact portion and a third contact portion both exposed on a lower surface of the first inner wall. The second contact portion is located closer to the second inner wall relative to the higher surface. In a vertical direction, the third contact portion is located farther away from the second inner wall relative to the higher surface. The second contact portion is grounded and conductively connected to the first electrical component inside the mating slot to form a first ground loop. The first contact portion is conductively connected to the first ground loop.
    Type: Application
    Filed: May 26, 2020
    Publication date: January 21, 2021
    Inventors: Jin Yi Tu, Shih Chi Kuan, Yu Chien Lin