Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: A method for checking standard cell spacing in a design includes providing a first standard cell. A cell environment of the first standard cell is determined and a first feasible distance between a first boundary of the standard cell and a boundary of a first adjacent cell based on the cell environment is determined. A second feasible distance between a second boundary of the standard cell and a boundary of a second adjacent cell based on the cell environment is determined. A feasible spacing between the first standard cell and a second standard cell is provided, and the feasible spacing is evaluated based on the first feasible distance, the second feasible distance and a cell pitch of the first standard cell. An integrated circuit is fabricated that includes the first standard cell in response on the evaluating.

Abstract: A manufacturing method of a transformer includes: winding a first winding wire around a bobbin, wherein two ends of the first winding wire are connected to a first and a second pin of the bobbin respectively; winding a second winding wire around the bobbin, wherein two ends of the second winding wire are connected to a third and a fourth pin of the bobbin respectively; and winding a third and a fourth winding wire in parallel around the bobbin, wherein two ends of the third winding wire are connected to the second and a fifth pin of the bobbin respectively, and two ends of the fourth winding wire are connected to the fifth and a sixth pin respectively. The first, the third and the fourth winding wires form a primary coil, and the second winding wire is a secondary coil.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first capacitor conductor disposed over an isolation structure arranged within a substrate. The isolation structure laterally extends past opposing outer sidewalls of the first capacitor conductor. A capacitor dielectric is arranged along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor. A second capacitor conductor is arranged along an outer sidewall of the capacitor dielectric and over a top surface of the capacitor dielectric. The second capacitor conductor laterally overlaps parts of both the capacitor dielectric and the first capacitor conductor.

Abstract: A redistribution structure is made using filler-free insulating materials with high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Abstract: A spatial light modulator device includes an array of spatial light modulator cells located over a substrate. Each of the spatial light modulator cells includes: a layer stack including a phase change material plate, a spacer dielectric material plate that underlies the phase change material plate, and a metallic heater plate underlying the spacer dielectric material plate and including outer sidewalls; and a pair of bottom electrode via structures contacting a respective surface segment of a bottom surface of the metallic heater plate. Each of the outer sidewalls of the metallic heater plate is vertically coincident with a respective sidewall of the spacer dielectric material plate and with a respective sidewall of the phase change material plate.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: According to an aspect of the disclosure, the disclosure provides an ADC which includes not limited to: a DAC configured to generate a positive input delta voltage and a negative input delta voltage, a comparator electrically connected to the DAC and configured to receive the positive input delta voltage to generate a first digital output value and to receive the negative input delta voltage to generate a second digital output value, a logic circuit configured to receive, from the comparator, the first digital output value and the second digital output value to generate a digital quantization code according to half of a sum of the first digital output value and the second digital output value, and a calibration circuit configured to receive the digital quantization code from the logic circuit and calibrate an output of the ADC according to the digital quantization code to eliminate an offset error value.

Abstract: A method of manufacturing an electronic device is provided. The method includes providing a substrate, disposing a composite conductive layer on the substrate, and patterning the composite conductive layer into a composite conductive pattern in two wet etching steps. Moreover, the two wet etching steps use different etching solutions.

Abstract: A semiconductor structure includes a substrate, an isolation structure disposed in the substrate, and a hybrid structure disposed over the isolation structure. The hybrid structure is substantially conformal with respect to a profile of the isolation structure. The hybrid structure includes an oxide component, a nitride component surrounding the oxide component, and a first polysilicon component alongside the nitride component. The nitride component includes a first upper surface closed to the first polysilicon component, and a second upper surface distal to the first polysilicon component. The second upper surface is lower than the first upper surface.

Abstract: The present disclosure provides a fusion protein and the nucleic acid encoding sequence thereof, and uses of the same. The fusion protein of the present disclosure achieves the effect of treating cancer, immunoregulation and activating immune cells through various efficacy experiments.

Abstract: Provided is a device for transdermal delivery of drugs. The device includes a separable substrate and is loaded with dual drugs based on an interpenetrating polymer network hydrogel. Also provided are methods of making and using the transdermal delivery device.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Abstract: The present invention relates to a basalt fiber reinforced concrete, which includes: a cement slurry with a water-to-cement ratio between 0.3 and 0.5, and a slurry volume percentage between 15-25%; an aggregate with an aggregate volume percentage between 65% and 75%; a basalt fiber reinforcement with a fiber volume percentage between 0.2% and 1.00%; and a concrete admixture used to adjust the properties of the basalt fiber reinforced concrete.

Abstract: The present invention relates to a basalt fiber reinforced asphalt concrete, which includes: an asphalt material with a penetration grade between 40-300 at room temperature, selected from one of an asphalt mortar, an oil-soluble asphalt, an emulsified asphalt, and a modified asphalt; an aggregate having a first volume percentage between 50-80%; a basalt fiber reinforcement with a second volume percentage between 0.1-0.9%; and a chemical admixture for asphalt concrete used to adjust the properties of the basalt fiber reinforced asphalt concrete.

Abstract: The present invention disclose a medical image-based system for predicting lesion classification and a method thereof. The system comprises a feature data extracting module for providing a raw feature data based on a medical image, and a predicting module for outputting a predicted class and a risk index according to the raw feature data. The predicting module comprises a classification unit for generating the predicted class and a prediction score corresponding thereto according to the raw feature data, and a risk evaluation unit for generating the risk index according to the prediction score. The system provides medical personnels a reference score and a risk index to determine progression of a certain disease.

Abstract: A refrigerant system including a compressor, an oil separator, an oil solenoid valve, a condenser, an evaporator, a bypass pipe, and a bypass solenoid valve is disclosed. The oil separator is connected to an output end of the compressor. The oil solenoid valve is disposed between the oil cooler and the compressor. The condenser is connected to the oil separator. The evaporator is connected to the condenser. The bypass pipe has a first end and a second end opposite to the first end. The first end is connected between the oil separator and the condenser, and the second end is connected between the evaporator and an input end of the compressor. The bypass solenoid valve is disposed on the bypass pipe. A controlling method for the refrigerant system is also disclosed.

Abstract: An electronic device is provided. The electronic device includes a substrate, a first conductive layer, an insulating layer, and a second conductive layer. The first conductive layer is disposed on the substrate. The first conductive layer has a first connection wire and a second connection wire. In a cycle, the first connection wire transmits a positive polarity signal and the second connection wire transmits a negative polarity signal. The insulating layer is disposed on the first conductive layer. The second conductive layer is disposed on the insulating layer. The second conductive layer includes a plurality of portions covering the first connection wire and the second connection wire. In addition, the number of first connection wire covered by each of the plurality of portions is equal to the number of second connection wire covered by each of the plurality of portions.