Patents by Inventor Yu-Chih Chuang

Yu-Chih Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10640372
    Abstract: A method for fabricating a semiconductor device is disclosed. A semiconductor substrate comprising a MOS transistor is provided. A MEMS device is formed over the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: May 5, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Publication number: 20190345029
    Abstract: A method for fabricating a semiconductor device is disclosed. A semiconductor substrate comprising a MOS transistor is provided. A MEMS device is formed over the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Patent number: 10472232
    Abstract: A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Publication number: 20180162725
    Abstract: A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Patent number: 6613696
    Abstract: A method of forming a composite silicon oxide layer over a semiconductor device. The composite silicon oxide layer is formed between the semiconductor device and a doped silicate glass layer. The composite silicon oxide layer comprises two silicon oxide layers, each having a different silicon/oxide composition. The oxygen-rich oxide layer or silicon dioxide layer is formed directly above the semiconductor device, and the silicon-rich oxide layer is formed above the silicon dioxide layer next to the doped silicate glass layer. Both the silicon dioxide layer and the silicon-rich oxide layer are formed in the same plasma deposition chamber.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: September 2, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Hai-Hung Wen, Yu-Chih Chuang
  • Publication number: 20010048146
    Abstract: A method of forming a composite silicon oxide layer over a semiconductor device. The composite silicon oxide layer is formed between the semiconductor device and a doped silicate glass layer. The composite silicon oxide layer comprises two silicon oxide layers, each having a different silicon/oxide composition. The oxygen-rich oxide layer or silicon dioxide layer is formed directly above the semiconductor device, and the silicon-rich oxide layer is formed above the silicon dioxide layer next to the doped silicate glass layer. Both the silicon dioxide layer and the silicon-rich oxide layer are formed in the same plasma deposition chamber.
    Type: Application
    Filed: July 6, 2001
    Publication date: December 6, 2001
    Inventors: Hai-Hung Wen, Yu-Chih Chuang
  • Patent number: 6287909
    Abstract: A method of fabricating a buried contact in a static random access memory. A gate oxide layer, a first conducting layer and a masking layer are formed sequentially on a substrate. A buried contact opening is formed inside the gate oxide layer, the first conducting layer and the masking layer, which opening exposes a part of the substrate. An epitaxial layer is formed inside the buried contact opening, which epitaxial layer fills up the buried contact opening. After the masking layer is removed, a second conducting layer is formed above the substrate. A buried contact is formed in the substrate that is below the epitaxial layer. The gate oxide layer, the first conducting layer, the epitaxial layer and second conducting layer are patterned to expose a part of the substrate and a part of the buried contact. A source/drain is formed in the substrate and a part of the source/drain is mixed with a part of the buried contact.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: September 11, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Min Jen, Tse-Yi Lu, Yu-Chih Chuang
  • Patent number: 5830772
    Abstract: Although the spacers are formed on the sidewalls of gate electrode and words lines via the same steps of deposition and etch-back processes, only the spacers disposed at the sidewalls of the gate electrode are practical for fabricating peripheral devices with LDD structure, and such fabrication is impractical in the memory cell region. On the contrary, the region beneath the spacers disposed at the sidewalls of word lines will become the path through which leakage current flows. The present invention makes use a shielding layer to cover the second active region as a masking, and then removes the spacers disposed at the sidewalls of word lines. Afterwards, isolating regions are formed through one implantation procedure to thereby decrease leakage current and simplify the process flow.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: November 3, 1998
    Assignee: United MicroelectronicsCorp.
    Inventors: Che-Pin Tseng, Nai-Jen Yeh, Yu-Chih Chuang, Cheng-Chih Kung