Patents by Inventor Yu Chih Huang

Yu Chih Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12362274
    Abstract: A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.
    Type: Grant
    Filed: February 20, 2024
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 12334434
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 12334956
    Abstract: A data processing method for a DNN model includes: reading weights of transmission data; quantizing each weight into bits sequentially including first, second, third, and fourth-type bits; sequentially interleaving the first-type bit into a first bit set; sequentially interleaving each second-type bit into second bit sets and reading a second compression rate of each second bit set in response to the compressible second bit sets; interleaving the third-type bit into a third bit set and reading a third compression rate of the third bit set in response to the compressible third bit set; compressing each second bit set with the second compression rate, and compressing the third bit set with the third compression rate; sequentially coding the first bit set, each compressed second bit set, and the compressed third bit set to generate first encoded data corresponding to the transmission data; transmitting the first encoded data to an external device.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: June 17, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Chih Huang, Li-Yang Tseng
  • Patent number: 12300644
    Abstract: In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Chia-Li Lin, Yu-Chih Huang, Chen-Shien Chen
  • Patent number: 12287589
    Abstract: Cleaning equipment for an EUV wafer chuck or clamp, which removes particles that have accumulated between burls on the surface of the wafer chuck. The equipment includes a spinning bi-polar electrode placed in proximity to the surface, which can attract and adsorb the charged particle residue therefrom using its generated symmetric electric field when the wafer chuck is not in use.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: April 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chih Huang, Yu-Kai Chiou, Chieh-Jen Cheng, Li-Jui Chen
  • Patent number: 12260669
    Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang
  • Patent number: 12205860
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240386744
    Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Chih Huang, Chih-Hua Chen, Yu-Jen Cheng, Chih-Wei Lin, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240377762
    Abstract: A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a carrier layer, a storage layer having an energy storage device and a water storage device, a magnetic shielding layer disposed between the carrier layer and the storage layer, and a receiver disposed in a recess of the carrier layer and partially exposed from the carrier layer.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Huan CHEN, Yu-Chih HUANG, Ya-An PENG, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20240371776
    Abstract: A manufacturing method of a semiconductor package includes the following steps. A semiconductor die set is placed adjacent to a lower conductive via. The semiconductor die set and the lower conductive via are at least laterally encapsulated with a lower encapsulating material to form a lower encapsulated semiconductor device. A lower redistribution structure is formed over the lower encapsulated semiconductor device. A sensor die is placed adjacent to an upper conductive via, wherein the sensor die has a pad and a sensing region. The sensor die and the upper conductive via are encapsulated with an upper encapsulating material to form an upper encapsulated semiconductor device. An upper redistribution structure is formed over the upper encapsulated semiconductor device, wherein the upper redistribution structure is connected to the pad and reveals the sensing region of the sensor die.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Cheng Tseng, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu
  • Publication number: 20240363464
    Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Patent number: 12113022
    Abstract: A semiconductor package includes a lower encapsulated semiconductor device, a lower redistribution structure, an upper encapsulated semiconductor device, and an upper redistribution structure. The lower redistribution structure is disposed over and electrically connected to the lower encapsulated semiconductor device. The upper encapsulated semiconductor device is disposed over the lower encapsulated semiconductor device and includes a sensor die having a pad and a sensing region, an upper encapsulating material at least laterally encapsulating the sensor die, and an upper conductive via extending through the upper encapsulating material and connected to the lower redistribution structure. The upper redistribution structure is disposed over the upper encapsulated semiconductor device. The upper redistribution structure covers the pad of the sensor die and has an opening located on the sensing region of the sensor die.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Cheng Tseng, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu
  • Patent number: 12111582
    Abstract: A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a base layer, a magnetic shielding layer disposed on the base layer, a carrier layer disposed on the magnetic shielding layer, a receiver disposed on the carrier layer, a storage layer disposed between the base layer and the magnetic shielding layer, and a magnetic shielding element disposed on the carrier layer and surrounding the receiver.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Huan Chen, Yu-Chih Huang, Ya-An Peng, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: 12114411
    Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. In some embodiments, a nozzle tube is arranged within the nozzle of the droplet generator, and the nozzle tube includes a structured nozzle pattern configured to provide an angular momentum to the target droplets.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Huan Chen, Yu-Chih Huang, Ming-Hsun Tsai, Shang-Chieh Chien, Heng-Hsin Liu
  • Publication number: 20240321780
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.
    Type: Application
    Filed: June 4, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20240297163
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: May 12, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Publication number: 20240290734
    Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan TAI, Ting-Ting KUO, Yu-Chih HUANG, Chih-Wei LIN, Hsiu-Jen LIN, Chih-Hua CHEN, Ming-Da CHENG, Ching-Hua HSIEH, Hao-Yi TSAI, Chung-Shi LIU
  • Patent number: 12068212
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Publication number: 20240204804
    Abstract: A data processing method for a DNN model includes: reading weights of transmission data; quantizing each weight into bits sequentially including first, second, third, and fourth-type bits; sequentially interleaving the first-type bit into a first bit set; sequentially interleaving each second-type bit into second bit sets and reading a second compression rate of each second bit set in response to the compressible second bit sets; interleaving the third-type bit into a third bit set and reading a third compression rate of the third bit set in response to the compressible third bit set; compressing each second bit set with the second compression rate, and compressing the third bit set with the third compression rate; sequentially coding the first bit set, each compressed second bit set, and the compressed third bit set to generate first encoded data corresponding to the transmission data; transmitting the first encoded data to an external device.
    Type: Application
    Filed: November 29, 2023
    Publication date: June 20, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Chih Huang, Li-Yang Tseng
  • Patent number: 12015017
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai