Patents by Inventor Yu Chih Lin

Yu Chih Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230288609
    Abstract: An optical structure, comprising an optical film having a substrate, wherein a first plurality of multi-faceted recesses are formed on the top surface of the substrate, wherein a prism module is disposed over the first optical film, wherein the prism module comprises a plurality of prism sheets that are stacked and bonded to each other.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 14, 2023
    Inventors: CHING-AN YANG, Lung-Pin Hsin, Hui-Yong Chen, Chien-Chih Lai, Yu-Mei Juan, Chia-Yeh Miu, Ge-Wei Lin, Ming Te Huang, CHENG CHIEH CHIU, WEN JEN WU
  • Publication number: 20230268446
    Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 24, 2023
    Inventors: Yu-Chun SHEN, Chi-Chung JEN, Ya-Chi HUNG, Yu-Chu LIN, Wen-Chih CHIANG
  • Publication number: 20230253508
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Application
    Filed: April 15, 2023
    Publication date: August 10, 2023
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Wen-Chih CHIANG, Yi-Ling LIU, Huai-jen TUNG, Keng-Ying LIAO
  • Publication number: 20230244305
    Abstract: An active interactive navigation system includes a display device, a target object image capturing device, a user image capturing device, and a processing device. The target object image capturing device captures a dynamic object image. The user image capturing device obtains a user image. The processing device recognizes and selects a service user from the user image and captures a facial feature of the service user. If the facial feature matches facial feature points, the processing device detects a line of sight of the service user and accordingly recognizes a target object watched by the service user, generates face position three-dimensional coordinates corresponding to the service user, position three-dimensional coordinates corresponding to the target object, and depth and width information, accordingly calculates a cross-point position where the line of sight passes through the display device, and display virtual information of the target object on the cross-point position of the display device.
    Type: Application
    Filed: January 5, 2023
    Publication date: August 3, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Te-Chih Liu, Ting-Hsun Cheng, Yu-Ju Chao, Jian-Lung Chen, Yu-Hsin Lin
  • Publication number: 20230238275
    Abstract: A method of forming a semiconductor device includes forming a plurality of non-insulator structures on a substrate, the plurality of non-insulator structures being spaced apart by trenches, forming a sacrificial layer overfilling the trenches, reflowing the sacrificial layer at an elevated temperature, wherein a top surface of the sacrificial layer after the reflowing is lower than a top surface of the sacrificial layer before the reflowing, etching back the sacrificial layer to lower the top surface of the sacrificial layer to fall below top surfaces of the plurality of non-insulator structures, forming a dielectric layer on the sacrificial layer, and removing the sacrificial layer to form air gaps below the dielectric layer.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chih HO, Yu-Chung SU, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20230236929
    Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
  • Publication number: 20230223480
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Application
    Filed: February 27, 2023
    Publication date: July 13, 2023
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, Chia-Wei LEE, Kuan-Wei SU, Chia-Ming PAN
  • Patent number: 11685784
    Abstract: The present disclosure provides an anti-immune-checkpoint nanobody that specifically binds to a programmed cell death ligand 1. The present disclosure also provides the nucleic acid sequence of the anti-immune-checkpoint nanobody, use of the anti-immune-checkpoint nanobody for treating cancer and immune-related disorders, and a method for detecting expression levels of PD-L1.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: June 27, 2023
    Assignee: CHINA MEDICAL UNIVERSITY HOSPITAL
    Inventors: Der-Yang Cho, Shao-Chih Chiu, Shi-Wei Huang, Chih-Ming Pan, Mei-Chih Chen, Yu-Chuan Lin, Yeh Chen
  • Patent number: 11682736
    Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chun Shen, Chi-Chung Jen, Ya-Chi Hung, Yu-Chu Lin, Wen-Chih Chiang
  • Patent number: 11677400
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lun Ou, Ji-Yung Lin, Yung-Chen Chien, Ruei-Wun Sun, Wei-Hsiang Ma, Jerry Chang Jui Kao, Shang-Chih Hsieh, Lee-Chung Lu
  • Publication number: 20230168416
    Abstract: An optical film, comprising a substrate, wherein a first plurality of multi-faceted recesses are formed on the substrate, wherein the plurality of multi-faceted recesses are capable of scattering lights that enter into a second surface of the substrate, said first surface and said second surface are two opposite surfaces of the substrate.
    Type: Application
    Filed: October 28, 2022
    Publication date: June 1, 2023
    Inventors: CHING-AN YANG, Lung-Pin Hsin, Hui-Yong Chen, Chien-Chih Lai, Yu-Mei Juan, Chia-Yeh Miu, Ge-Wei Lin, Ming Te Huang, CHENG CHIEH CHIU, WEN JEN WU
  • Patent number: 11658248
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Yi-Ling Liu, Wen-Chih Chiang, Keng-Ying Liao, Huai-jen Tung
  • Patent number: 11650420
    Abstract: A head-up display including a light source module, a spatial light modulator, an imaging screen group and a control unit is provided. The light source module is configured to project a light beam. The spatial light modulator is configured to modulate the light beam as a first image and a second image and project respective image lights of the first and second images. The imaging screen group is configured to reflect the image lights of the first and second images to the visible range of the user, such that the user can view the first and second images. The control unit is coupled to the spatial light modulator to input at least two modulation signals to control the beam-splitting mechanism of the spatial light modulator.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: May 16, 2023
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Yu-Chih Lin, Ming-Ping Lai
  • Patent number: 11630602
    Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).
    Type: Grant
    Filed: January 16, 2022
    Date of Patent: April 18, 2023
    Assignee: Silicon Motion, Inc.
    Inventor: Yu-Chih Lin
  • Publication number: 20230105741
    Abstract: Compositions including photoreactive and cleavable probes and methods of using the probes. The probes may include a tag conjugatable to a label, a cleavable linker linkable to a bait molecule, and a light-activated warhead. The compositions and methods may be useful for analyzing biomolecules.
    Type: Application
    Filed: September 19, 2022
    Publication date: April 6, 2023
    Inventors: Hsiao-Jen CHANG, Yi-De CHEN, Chih-Wei CHANG, Chantal Hoi Yin CHEUNG, Yu-Chih LIN, Chia-Wen CHUNG, Hsiang-Ju KAI
  • Patent number: 11579447
    Abstract: A head-up display capable of adjusting an imaging position is provided. The head-up display includes an image generation module, a reflector, a holographic diffraction optical element and a control unit. The image generation module is configured to display and project an image. The reflector is configured to reflect the image and further project the image on a transparent screen through the reflector. The holographic diffraction optical element is disposed on the transparent screen to reflect the image to a visible range of the user's eyes. The control unit is coupled to the reflector or the transparent screen to adjust the viewing angle of the holographic diffraction optical element having a pre-determined angle with the reflector.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: February 14, 2023
    Inventors: Yu-Chih Lin, Tzu-Nan Chen, Ming-Ping Lai
  • Publication number: 20220137871
    Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).
    Type: Application
    Filed: January 16, 2022
    Publication date: May 5, 2022
    Applicant: Silicon Motion, Inc.
    Inventor: Yu-Chih Lin
  • Patent number: 11262938
    Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: March 1, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Yu-Chih Lin
  • Patent number: 11249685
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each clock includes a plurality of pages, and the method includes the steps of: providing a read-retry table, wherein the read-retry table includes a plurality of read setting levels, each read setting level corresponds to at least one read voltage, and no two read setting levels have the same read voltage; establishing a read success recording table, which records at least one specific read setting level that was previously used to successfully read the flash memory module; and when it is required to the read the flash memory module, using the at least one specific read setting level recorded in the read success recording table to read the flash memory module.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 15, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Yu-Chih Lin
  • Publication number: 20210349655
    Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).
    Type: Application
    Filed: October 28, 2020
    Publication date: November 11, 2021
    Inventor: Yu-Chih Lin