Abstract: A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement.

Abstract: A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.

Abstract: An insulated structure of a chip array component and fabrication method of the same, the element is fabricated by enclosing its main body with a dense layer of high surface insulation resistance material, and then exposing the portions of the main body where terminal electrodes are to be formed by removing the dense layer of high surface insulation resistance material by employing sand blasting, laser trimming, grinding, or etching process.

Abstract: Described herein is a system for verifying that a circuit described by a hardware description language file has a property of responding to an antecedent event represented by a particular pattern in its input signals by exhibiting a consequent behavior of producing a particular pattern in its output signals during a finite time following the antecedent event. The system includes a conventional circuit simulator for simulating the behavior of the circuit under conditions defined by a user-provided test bench. The simulator produces output waveform data representing the behavior of the circuit input, output and internal signals, including signals representing the circuit's state. When the output waveform data indicates the antecedent event has occurred, the system determines the current state of the circuit from the waveform data.

Abstract: A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.