Abstract: Dynamic sampling systems for fabrication with inspection control are provided. In embodiments of a fabrication system comprising a processing tool, inspection tool, and a controller, the processing tool performs a fabrication process on a workpiece associated with identification information. The inspection tool performs an inspection step on the workpiece. The controller, coupled to the processing and inspection tools, determines whether the processing tool corresponds to an inspection result obtained during a preset time period, and determines whether the workpiece is to be inspected by the inspection tool accordingly.

Abstract: A protection circuit is coupled between a secondary winding of a transformer and a load. When voltage at the secondary winding of the transformer becomes abnormal, the protection circuit disconnects the power connection to the load so as to protect the load from damage. When the voltage at the secondary winding of the transformer returns normal, the protection circuit restores power to the load.

Abstract: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

Abstract: Within a method for forming a microelectronic fabrication there is provided a substrate having formed thereover a patterned dielectric layer which defines a via. There is also formed within a lower portion of the via a tungsten stud layer having a recess thereabove within the via. There is also formed within the recess a patterned conductor capping layer formed of a conductor material other than tungsten. The patterned conductor capping layer may seal a void formed within the tungsten stud layer.

Abstract: A derailleur system for bicycle is constructed to include an annular plate holding at least two gears, a bracket assembly rotated to a center hole of the annular plate to hold a transmission shaft, a driven gear wheel set pivoted to the transmission shaft and having a driven gear wheel meshed with one of the gears, a control device connected to a derailleur cable of the bicycle, and a driven member for selectively controlling the engagement between the driven gear wheels of the driven gear wheel set with the transmission shaft subject to the position of the control device.

Abstract: A fuse structure and method for fabricating same are disclosed. The fuse structure is designed for opening by conventional laser energy application. The fuse structure is characterized by an absence of high stress areas in the surrounding substrate thereby resulting in higher fabrication yields due to lower occurrence of substrate fracturing or other damage occasioned by the opening of the fuse.

Abstract: A derailleur system for bicycle is constructed to include an annular plate holding at least two gears, a bracket assembly rotated to a center hole of the annular plate to hold a transmission shaft, a driven gear wheel set pivoted to the transmission shaft and having a driven gear wheel meshed with one of the gears, a control device connected to a derailleur cable of the bicycle, and a driven member for selectively controlling the engagement between the driven gear wheels of the driven gear wheel set with the transmission shaft subject to the position of the control device.

Abstract: Within a method for forming a microelectronic fabrication there is provided a substrate having formed thereover a patterned dielectric layer which defines a via. There is also formed within a lower portion of the via a tungsten.stud layer having a recess thereabove within the via. There is also formed within the recess a patterned conductor capping layer formed of a conductor material other than tungsten. The patterned conductor capping layer may seal a void formed within the tungsten stud layer.

Abstract: A fuse structure and method for fabricating same are disclosed. The fuse structure is designed for opening by conventional laser energy application. The fuse structure is characterized by an absence of high stress areas in the surrounding substrate thereby resulting in higher fabrication yields due to lower occurrence of substrate fracturing or other damage occasioned by the opening of the fuse.

Abstract: A device for retaining the shape of a shoe includes a tapering base member having an arch cross section and a shoe expansion member defining a cavity removably receiving the base member therein. The base member has opposite side walls and an arcuated top wall defining a groove in which a stair-like configuration is formed, having a first number of steps. The side walls of the base member each form first serration. The shoe expansion member has a bottom in which the cavity is defined and a top side configured to closely fit into a shoe for retaining the shape of the shoe. The cavity is defined by opposite side walls and a top wall. The top wall of the cavity has a stair-like structure having a second number of steps. The side walls of the cavity form second serration. The stair-like structure of the cavity is at least partially engageable with and supported by the stair-like configuration of the top wall of the base member.

Abstract: A method to provide low dielectric constant voids between adjacent conducting lines in a semiconductor device. Narrowly spaced metal lines are formed on the substrate surface. A dielectric layer is deposited overlying the metal lines and the substrate surface. A high water content, water saturated, environment is created for the spin-on-glass process. A pseudo-water condition exists on the surface of the dielectric layer prior to the deposition of the spin-on-glass layer. The spin-on-glass layer is deposited overlying the dielectric layer. Voids form in the spin-on-glass layer between the narrowly spaced metal lines. The spin-on-glass layer is baked. The integrated circuit device is completed.