Patents by Inventor Yu-Ching Chen

Yu-Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240146205
    Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.
    Type: Application
    Filed: September 23, 2023
    Publication date: May 2, 2024
    Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240137709
    Abstract: An electro-acoustical transducer device is disclosed, which includes: a hollow disk body that generally defines an axis of propagation, the hollow disk body comprising: a pair of plate members extending substantially perpendicular to the axis of propagation, each provided with a central transmitting port arranged about the axis of propagation, and a peripheral enclosure jointing the pair of plate members at the respective outer edge portions thereof, thereby defining a chamber of resonance between the pair of plate members; wherein a ring-opening about the axis of propagation that enables access to the chamber of resonance is formed between the central transmitting ports of the plate members.
    Type: Application
    Filed: April 27, 2023
    Publication date: April 25, 2024
    Inventors: YU-CHEN CHEN, CHUN-KAI CHAN, HSU-HSIANG CHENG, MING-CHING CHENG
  • Patent number: 11967375
    Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Yu-Sheng Chen, Hon-Sum Philip Wong
  • Patent number: 11963369
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen
  • Publication number: 20240113222
    Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.
    Type: Application
    Filed: January 3, 2023
    Publication date: April 4, 2024
    Inventors: Yan-Yi Chen, Wu-Wei Tsai, Yu-Ming Hsiang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240113225
    Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Wei Tsai, Yan-Yi Chen, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11931867
    Abstract: The present invention relates to a socket used in coordination with a wrench. The socket includes a socket main body which has a head portion and a body portion connected to the head portion. The head portion is adapted for being coupled with the wrench. The body portion has a polygonal hole for being coupled with a head portion of a bolt or a nut, so that the wrench is adapted for screwing on or off the bolt or nut through the socket main body. Besides, a pipe made of composite material is sleeved onto the external peripheral surface of the body portion. The pipe is freely detachable, and the external peripheral surface of the pipe can be provided with a print, pattern, color or character according to the practical demands, thereby attaining the effects of high variability in appearance, great durability and great recognizability.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 19, 2024
    Inventor: Yu-Ching Chen
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Publication number: 20230418112
    Abstract: A liquid crystal phase modulation device includes a first substrate, a second substrate opposite to the first substrate, a liquid crystal layer, a first alignment layer, and a first spacer. The liquid crystal layer is between the first substrate and the second substrate. The first alignment layer is adjacent to the liquid crystal layer and having a first alignment direction. The first spacer is between the first substrate and the second substrate. The first spacer has a diamond shape in a top view, and the diamond shape of the first spacer has a first length in the first alignment direction and a second length in a direction perpendicular to the first alignment direction in the top view, and the first length is greater than the second length.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Inventors: Chih-Chan LIN, Yu-Ching CHEN
  • Patent number: 11789319
    Abstract: A liquid crystal phase modulation device includes a first substrate, a second substrate, a liquid crystal layer, at least one first spacer, and a first alignment layer. The second substrate is opposite to the first substrate. The liquid crystal layer is between the first substrate and the second substrate. The one first spacer is between the first substrate and the second substrate. The first alignment layer is adjacent to the liquid crystal layer and the first spacer, and has a first alignment direction. The first spacer has a first length in the first alignment direction and a second length in a direction perpendicular to the first alignment direction as view from top, and the first length is greater than the second length.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 17, 2023
    Assignee: Liqxtal Technology Inc.
    Inventors: Chih-Chan Lin, Yu-Ching Chen
  • Patent number: 11765881
    Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: September 19, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Ting Ho, Ying-Chiao Wang, Yu-Ching Chen, Hui-Ling Chuang, Kuei-Hsuan Yu
  • Patent number: 11639145
    Abstract: A vehicle structure material strengthening system and a vehicle containing the same are described. The vehicle structure material strengthening system has at least one collision sensor, a processor, and a power supply. The collision sensor is suitable for being mounted on the vehicle. The processor is electrically connected to the collision sensor for receiving a collision signal from the collision sensor, and determines whether to transmit a power activation signal according to the collision signal. The power supply is electrically connected to the processor and the vehicle. When the collision signal is greater than or equal to a collision threshold, the processor transmits the power activation signal to the power supply, wherein the power supply transmits a circuit to the vehicle according to the power activation signal; or when the collision signal is less than the collision threshold, the processor does not transmit the power activation signal.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 2, 2023
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Shih-Kang Lin, Yu-Chen Liu, Yu-Ching Chen, Kuan-Hsueh Lin
  • Publication number: 20230097175
    Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 30, 2023
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Ting Ho, Ying-Chiao Wang, Yu-Ching Chen, Hui-Ling Chuang, Kuei-Hsuan Yu
  • Patent number: 11615511
    Abstract: A method of removing raindrops from video images is provided. The method includes the steps of: training a raindrop image recognition model using a plurality raindrop training images labeled in a plurality of rainy-scene images; recognizing a plurality of raindrop images from a plurality of scene images in a video sequence using the raindrop image recognition model; and in response to a specific raindrop image in a current scene image satisfying a predetermined condition, replacing the specific raindrop image in the current scene image with an image region corresponding to the specific raindrop image in a specific scene image prior to the current scene image to generate an output scene image.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: March 28, 2023
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chien-Hung Lin, Yang-Sheng Wang, Yu-Ching Chen, Chih-Tsang Yeh, Po-An Yang
  • Patent number: 11563012
    Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 24, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Ting Ho, Ying-Chiao Wang, Yu-Ching Chen, Hui-Ling Chuang, Kuei-Hsuan Yu
  • Patent number: 11557021
    Abstract: A positioning system includes a storage device, a lidar and a controller. The storage device stores a global map. The lidar generates an initial local map. The controller rotates the initial local map to generate a rotated local map, compares the rotated local map and the initial local map separately with a plurality of partial areas of the global map, so as to obtain at least one similar area, calculates at least one candidate coordinates for a mobile device on the global map according to the center point of each of the similar areas, and calculates similarity scores according to each of the candidate coordinates, and selects the candidate coordinates having highest similarity score for use as coordinate of the mobile device on the global map.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: January 17, 2023
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Yi Liu, Chia-Wei Lin, Yang-Sheng Wang, Chun-Ting Chen, Yu-Ching Chen
  • Patent number: 11487167
    Abstract: A method for fabricating a liquid crystal phase modulation device is provided. The method includes detecting thicknesses of a plurality of portions of a reference liquid crystal layer of a reference liquid crystal phase modulation sample; determining a distribution according to the thicknesses of the portions of the reference liquid crystal layer; forming a plurality of spacers over a first substrate in the determined distribution; and combining the first substrate with a second substrate and a liquid crystal layer to form the liquid crystal phase modulation device.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 1, 2022
    Assignee: Liqxtal Technology Inc.
    Inventors: Chih-Chan Lin, Yu-Ching Chen
  • Patent number: 11436507
    Abstract: Nodes of a weighted tree each have their own weight. A normalized weight of a node, relative to other nodes in the tree, is determined based on a proportional weight of the node and a lesser unique sum of the node, as well as those of the node's parents and grandparents, up to a root of the tree. The proportional weight and lesser unique sum of a given node depend only on the unique weights of the sibling group including the given node. Thus, if a weight is modified, the normalized weight can be updated without necessarily recalculating the entire tree.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ching Chen, Tuo Wang, Ziyue Jason Wang, Lior Aronovich