Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first active region extending lengthwise along a first direction and having a first width along a second direction perpendicular to the first direction, a second active region extending lengthwise along the first direction and having a second width along the second direction, and an epitaxial feature sandwiched between the first active region and the second active region along the first direction. The first width is greater than the second width.

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: A wafer transporting method includes following operations. A plurality of wafers are received in a semiconductor container attached to a mobile vehicle. An air processing system is coupled to a wall of the semiconductor container. The air processing system includes an inlet valve, an outlet valve, a pump between the inlet valve and the outlet valve, and a desiccant coupled to the pump. The semiconductor container is moved. The pump of the air processing system is turned on to extract air from inside the semiconductor container into the air processing system through the inlet valve. Humidity of the air is reduced when the air passes through the desiccant of the air processing system. The air is returned back to the semiconductor container through the outlet valve.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A torsion tool is provided, including: a barrel; a first member disposed at one end of the barrel, including at least one first engaging portion; a second member, disposed in the barrel, including at least one second engaging portion releasably engaged with the at least one first engaging portion; an elastic mechanism, including a first fixation portion disposed in the barrel and elastic arms, the elastic arms being independently fixed to the first fixation portion and corresponding to each other, the second member being located between and configured to radially expand the elastic arms; wherein as the second member urges and radially expands the elastic arms, the at least one second engaging portion and the at least one first engaging portion are relatively slipable and disengageable.

Abstract: A human resource scheduling method and an electronic apparatus for scheduling human resources are provided. A test model is constructed based on a test objective function and a plurality of test constraint formulas. The test model is applied to substitute set data into the test constraint formulas, so that the test constraint formulas are applied to find a solution based on the test objective function to determine whether the set data are valid based on the solution. In response to the test model determining that the set data are valid, the set data is input into an optimization model to obtain a human resource scheduling plan.

Abstract: The present disclosure provides a method capable of switching display modes with a display screen having a plurality of pixels. The method includes: providing a selection interface on the display, wherein the selection interface provides a first display setting and a second display setting; determining whether the first display setting or the second display setting is selected, wherein when the first display setting is selected, the controller controls to display an image content with the plurality of pixels of the display; when the second display setting is selected, the plurality of pixels of the display are merged into a plurality of merges Pixel group to display image content.

Abstract: The present invention provides a polybenzoxazole precursor, which comprises a structure of formula (I): wherein the definitions of Y, Z, R1, i, j, and V are provided herein. By means of the polybenzoxazole precursor, the resin composition of the present invention is able to form a film with high frequency characteristics and high contrast.

Abstract: A torque tool is provided, including: a barrel; a first member disposed to the barrel, including at least one first engaging portion; a second member disposed in the barrel, including at least one second engaging portion, the at least one second engaging portion and the at least one first engaging portion being disengageably engaged with each other; an elastic mechanism, disposed inside the barrel and including elastic arms, the second member being configured to abut and radially deform the elastic arms; wherein when there is a torsional three greater than a preset torque value between the at least one second engaging portion and the at least one first engaging portion, the second member urges and radially defines the plurality of elastic arms so that the at least one second engaging portion and the at least one first engaging portion are relatively slipable and disengageable.

Abstract: A torque tool is provided, including: a barrel; a first member disposed to the barrel, including at least one first engaging portion; a second member disposed in the barrel, including at least one second engaging portion, the at least one second engaging portion and the at least one first engaging portion being disengageably engaged with each other; an elastic mechanism, disposed inside the barrel and including elastic arms, the second member being configured to abut and radially deform the elastic arms; wherein when there is a torsional three greater than a preset torque value between the at least one second engaging portion and the at least one first engaging portion, the second member urges and radially defines the plurality of elastic arms so that the at least one second engaging portion and the at least one first engaging portion are relatively slipable and disengageable.

Abstract: The present invention provides a pin retainer comprising a base, and a retaining structure coupled to the base. The base has a through slot, two through-holes respectively formed at two opposite sides of an opening of the through-slot formed on a surface of the base for respectively accommodating guide pins, and first engaging structures respectively formed on two lateral surfaces of the base. The retaining structure has a pair of lateral plates slidably coupled to the two lateral surfaces. Each lateral plate has second engaging structure corresponding to the first engaging structure, and a positioning plate having a holding structure. The second engaging structure is combined with or released from the first engaging structure depending on the positions of the retaining structure. Alternatively, the present invention also presents an optical connector using the pin retainer.