Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.

Abstract: A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A memory cell includes a dielectric structure, a storage element structure, and a top electrode. The storage element structure is disposed in the dielectric structure, and the storage element structure includes a first portion and a second portion. The first portion includes a first side and a second side opposite to the first side, where a width of the first side is less than a width of the second side. The second portion is connected to the second side of the first portion, where a width of the second portion is greater than the width of the first side. The top electrode is disposed on the storage element structure, where the second portion is disposed between the first portion and the top electrode.

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Abstract: A high-speed connector includes an insulating housing, and at least one terminal assembly disposed in the insulating housing. The at least one terminal assembly includes a base body, a plurality of terminals fastened to the base body, and a metal block. A surface of the base body is recessed inward to form a fastening groove. The plurality of the terminals include a plurality of grounding terminals and differential signal terminals. Each of the plurality of the grounding terminals and the differential signal terminals has a fastening portion. The fastening portions of at least several of the plurality of the grounding terminals and the differential signal terminals are exposed to the fastening groove. The metal block is fastened in the fastening groove. The fastening portions of the grounding terminals which are exposed to the fastening groove are electrically connected with the metal block to form a grounding structure.

Abstract: A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.

Abstract: The present invention discloses a vessel power safety control system and operating method thereof. The vessel power safety control system includes a load power management module, a real-time monitoring module, an integration module and a power module. The present invention can assist the autonomous ship as any occurrence of fault during navigation. Once the accident occurs, the load power management module will give an instruction to control the DC bus to switch from closed circuit to open circuit to protect other equipment. After determining whether the errors of the equipment on board is eliminated, the load power management system performs automatic system reset procedure. As such, the DC bus can be converted from an open circuit to a closed circuit to restart the power supply for the facility.

Abstract: The present invention relates to a basalt fiber reinforced concrete, which includes: a cement slurry with a water-to-cement ratio between 0.3 and 0.5, and a slurry volume percentage between 15-25%; an aggregate with an aggregate volume percentage between 65% and 75%; a basalt fiber reinforcement with a fiber volume percentage between 0.2% and 1.00%; and a concrete admixture used to adjust the properties of the basalt fiber reinforced concrete.

Abstract: The present invention relates to a basalt fiber reinforced asphalt concrete, which includes: an asphalt material with a penetration grade between 40-300 at room temperature, selected from one of an asphalt mortar, an oil-soluble asphalt, an emulsified asphalt, and a modified asphalt; an aggregate having a first volume percentage between 50-80%; a basalt fiber reinforcement with a second volume percentage between 0.1-0.9%; and a chemical admixture for asphalt concrete used to adjust the properties of the basalt fiber reinforced asphalt concrete.

Abstract: A memory cell includes a bottom electrode, a first dielectric layer, a top electrode, and a variable resistance layer. The first dielectric layer laterally surrounds the bottom electrode. The top electrode is disposed over the bottom electrode and the first dielectric layer. The variable resistance layer is sandwiched between the bottom electrode and the top electrode and between the first dielectric layer and the top electrode. The variable resistance layer exhibits a T-shape in a cross-sectional view.

Abstract: The present invention provides a polybenzoxazole precursor, which comprises a structure of formula (I): wherein the definitions of Y, Z, R1, i, j, and V are provided herein. By means of the polybenzoxazole precursor, the resin composition of the present invention is able to form a film with high frequency characteristics and high contrast.

Abstract: A torsion tool is provided, including: a barrel; a first member disposed at one end of the barrel, including at least one first engaging portion; a second member, disposed in the barrel, including at least one second engaging portion releasably engaged with the at least one first engaging portion; an elastic mechanism, including a first fixation portion disposed in the barrel and elastic arms, the elastic arms being independently fixed to the first fixation portion and corresponding to each other, the second member being located between and configured to radially expand the elastic arms; wherein as the second member urges and radially expands the elastic arms, the at least one second engaging portion and the at least one first engaging portion are relatively slipable and disengageable.

Abstract: A human resource scheduling method and an electronic apparatus for scheduling human resources are provided. A test model is constructed based on a test objective function and a plurality of test constraint formulas. The test model is applied to substitute set data into the test constraint formulas, so that the test constraint formulas are applied to find a solution based on the test objective function to determine whether the set data are valid based on the solution. In response to the test model determining that the set data are valid, the set data is input into an optimization model to obtain a human resource scheduling plan.