Patents by Inventor Yu-Chiun Lin

Yu-Chiun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395802
    Abstract: A semiconductor structure includes a base structure, a first portion, a second portion and a first stack. The first portion and the second portion are disposed on the base structure and are respectively made of a first semiconductor material and a second semiconductor material which has a conductivity type opposite to that of the first semiconductor material. The first stack is disposed on the base structure and between the first portion and the second portion. The first stack includes a plurality of first semiconductor regions and a plurality of first dielectric regions disposed to alternate with the first semiconductor regions, such that each of the first semiconductor regions and the first dielectric regions extends between the first portion and the second portion. The first semiconductor regions has a dopant concentration which is lower than that of each of the first portion and the second portion.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dai-Yan WU, Yu-Chiun LIN, Po-Nien CHEN, Hsiao-Han LIU, Chih-Yung LIN
  • Publication number: 20240395803
    Abstract: A semiconductor structure includes a base structure, at least one diode device and a semiconductor device. The base structure has a first base region and a second base region. The at least one diode device includes a first feature formed in the first base region, and a second feature formed over the first feature and having a conductivity type opposite to that of the first feature. The semiconductor device is formed on the second base region.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dai-Yan Wu, Yu-Chiun Lin, Po-Nien CHEN, Hsiao-Han LIU, Chih-Yung LIN
  • Publication number: 20240355868
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chiun LIN, Po-Nien CHEN, Chen Hua TSAI, Chih-Yung LIN
  • Publication number: 20240321731
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
  • Patent number: 12057469
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
  • Patent number: 12033937
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
  • Publication number: 20210288137
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Yu-Chiun LIN, Po-Nien CHEN, Chen Hua TSAI, Chih-Yung LIN
  • Patent number: 11024703
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
  • Publication number: 20210066193
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
  • Patent number: 10840181
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
  • Publication number: 20200328270
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Yu-Chiun LIN, Po-Nien CHEN, Chen Hua TSAI, Chih-Yung LIN
  • Patent number: 10700160
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
  • Publication number: 20190341445
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Yu-Chiun LIN, Po-Nien CHEN, Chen Hua TSAI, Chih-Yung LIN
  • Patent number: 10411085
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
  • Patent number: 10355071
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
  • Publication number: 20190148293
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
  • Patent number: 10170414
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
  • Publication number: 20180190754
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.
    Type: Application
    Filed: May 12, 2017
    Publication date: July 5, 2018
    Inventors: Yu-Chiun LIN, Po-Nien CHEN, Chen Hua TSAI, Chih-Yung LIN
  • Publication number: 20170365552
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Application
    Filed: August 31, 2017
    Publication date: December 21, 2017
    Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
  • Patent number: 9773731
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen