Abstract: A display device includes a display panel including a pixel, a voltage line supplying a power voltage to the pixel, and a reference voltage line supplying one of a reference voltage and the power voltage to the pixel; a mode selector configured to output one of a first selection signal and a second selection signal according to an operation mode of the display panel; and a switch configured to provide the reference voltage or the power voltage to the reference voltage line in response to one of the first selection signal and the second selection signal.

Abstract: A display device driving method includes: providing a reference voltage for compensating a threshold voltage of a driving transistor in a pixel; and providing a data signal to the pixel, wherein providing the reference voltage, and providing the data signal to the pixel are performed in a first frame period, and a second frame period successive to the first frame period, wherein the display device driving method further comprises providing a compensation signal generated by comparing a data signal with a reference voltage provided in a previous frame period of each frame period to the pixel before providing the reference voltage is ended.

Abstract: A display device capable of setting an optimal output enable value according to a color pattern and a method for driving the display device. A timing controller is configured to receive an image signal from an external source, identify a color pattern and set an output enable value corresponding to the identified color pattern. A scan driver is configured to receive the output enable value and generate a first scan signal having a first turn-on signal and a second scan signal adjacent to the first scan signal and having a second turn-on signal. The scan driver may adjust an interval between the first turn-on signal and the second turn-on signal based on the output enable value.

Abstract: The present disclosure relates to a display device and a method of driving the same. The display device includes a substrate, a display panel including a first display area including first pixels, a second display area including second pixels, and a third display area disposed between the first and second display areas and including third pixels, and a component disposed between the substrate and the display panel so as to overlap the second display area. Transmittance of the second display area is higher than transmittance of the first display area and transmittance of the third display area, and the third pixels are controlled such that a luminance gradually changes according to a distance from the second display area.

Abstract: An embodiment provides a display device including: a light emitting diode; a driving transistor configured to supply a current to the light emitting diode; a switching transistor having an input electrode connected to a data line; and a voltage transmitting capacitor disposed between an output electrode of the switching transistor and a gate electrode of the driving transistor, wherein a data voltage applied to the data line may be transmitted to the gate electrode of the driving transistor through the voltage transmitting capacitor, and the data voltage may have a data voltage value from which a voltage variation variable is removed based on leakage of the switching transistor.

Abstract: A display device driving method includes: providing a reference voltage for compensating a threshold voltage of a driving transistor in a pixel; and providing a data signal to the pixel, wherein providing the reference voltage, and providing the data signal to the pixel are performed in a first frame period, and a second frame period successive to the first frame period, wherein the display device driving method further comprises providing a compensation signal generated by comparing a data signal with a reference voltage provided in a previous frame period of each frame period to the pixel before providing the reference voltage is ended.

Abstract: A display apparatus includes a display panel, a gate driver and a data driver. The display panel displays an image. The gate driver outputs gate signals to the display panel. The data driver outputs data voltages to the display panel. The data driver includes a plurality of data driving circuits. At least two data driving circuits among the data driving circuits have different turn off timings or different turn on timings in a vertical blank period.

Abstract: A display device capable of setting an optimal output enable value according to a color pattern and a method for driving the display device. A timing controller is configured to receive an image signal from an external source, identify a color pattern and set an output enable value corresponding to the identified color pattern. A scan driver is configured to receive the output enable value and generate a first scan signal having a first turn-on signal and a second scan signal adjacent to the first scan signal and having a second turn-on signal. The scan driver may adjust an interval between the first turn-on signal and the second turn-on signal based on the output enable value.

Abstract: A display device capable of setting an optimal output enable value according to a color pattern and a method for driving the display device. A timing controller is configured to receive an image signal from an external source, identify a color pattern and set an output enable value corresponding to the identified color pattern. A scan driver is configured to receive the output enable value and generate a first scan signal having a first turn-on signal and a second scan signal adjacent to the first scan signal and having a second turn-on signal. The scan driver may adjust an interval between the first turn-on signal and the second turn-on signal based on the output enable value.

Abstract: A display apparatus includes a gate driving control circuit, a gate driver and a display panel. The gate driving control circuit generates N gate clock signals and N inversion gate clock signals based on N gate clock control signals, phases of which partially overlap with each other. Each inversion gate clock signals has an opposite phase to a respective gate clock signal. The gate driver generates gate signals based on the N gate clock signals or the N inversion gate clock signals and applies the gate signals to gate lines. The display panel includes pixels, each connected to a respective gate line and a respective data line. Each of the pixels has a longer side in parallel with gate lines and a shorter side in parallel with the data lines. A number of the gate clock control signals is an integer multiple of a number of colors of the pixels.

Abstract: A display device includes a display panel, and a power management circuit including a switching regulator for supplying a power in a discontinuous conduction mode or in a continuous conduction mode, and a sensing circuit for sensing whether the switching regulator is operated in the discontinuous conduction mode, the switching regulator including a comparator for monitoring the supplied power, and an RS latch for receiving an output signal from the comparator, and the sensing circuit including a phase lock loop circuit for generating a first clock signal, a phase delay circuit for generating a second clock signal having a phase delayed from the first, and a determination circuit for outputting a first value when a pulse width of the output signal from the RS latch is small, and for outputting a second value when the pulse width of the output signal from the RS latch is not small.

Abstract: A display apparatus includes a display panel, a gate driver and a data driver. The display panel displays an image. The gate driver outputs gate signals to the display panel. The data driver outputs data voltages to the display panel. The data driver includes a plurality of data driving circuits. At least two data driving circuits among the data driving circuits have different turn off timings or different turn on timings in a vertical blank period.

Abstract: A clock generation circuit includes: a clock generator to receive a gate pulse signal and to generate at least one gate clock signal corresponding to the gate pulse signal; an over-current protector to detect a current level of the at least one gate clock signal, and to output a shutdown enable signal and at least one switching signal corresponding to the detected current level; and a switching unit including at least one switching device to output the gate pulse signal as the at least one gate clock signal. The clock generator is to generate the at least one gate clock signal in response to the shutdown enable signal, and the at least one switching device is to transmit the gate pulse signal as the at least one gate clock signal in response to the at least one switching signal.

Abstract: A display device includes a display panel, and a power management circuit including a switching regulator for supplying a power in a discontinuous conduction mode or in a continuous conduction mode, and a sensing circuit for sensing whether the switching regulator is operated in the discontinuous conduction mode, the switching regulator including a comparator for monitoring the supplied power, and an RS latch for receiving an output signal from the comparator, and the sensing circuit including a phase lock loop circuit for generating a first clock signal, a phase delay circuit for generating a second clock signal having a phase delayed from the first, and a determination circuit for outputting a first value when a pulse width of the output signal from the RS latch is small, and for outputting a second value when the pulse width of the output signal from the RS latch is not small.

Abstract: A display apparatus includes a gate driving control circuit, a gate driver and a display panel. The gate driving control circuit generates N gate clock signals and N inversion gate clock signals based on N gate clock control signals, phases of which partially overlap with each other. Each inversion gate clock signals has an opposite phase to a respective gate clock signal. The gate driver generates gate signals based on the N gate clock signals or the N inversion gate clock signals and applies the gate signals to gate lines. The display panel includes pixels, each connected to a respective gate line and a respective data line. Each of the pixels has a longer side in parallel with gate lines and a shorter side in parallel with the data lines. A number of the gate clock control signals is an integer multiple of a number of colors of the pixels.

Abstract: A display device capable of setting an optimal output enable value according to a color pattern and a method for driving the display device. A timing controller is configured to receive an image signal from an external source, identify a color pattern and set an output enable value corresponding to the identified color pattern. A scan driver is configured to receive the output enable value and generate a first scan signal having a first turn-on signal and a second scan signal adjacent to the first scan signal and having a second turn-on signal. The scan driver may adjust an interval between the first turn-on signal and the second turn-on signal based on the output enable value.

Abstract: A clock generation circuit includes: a clock generator to receive a gate pulse signal and to generate at least one gate clock signal corresponding to the gate pulse signal; an over-current protector to detect a current level of the at least one gate clock signal, and to output a shutdown enable signal and at least one switching signal corresponding to the detected current level; and a switching unit including at least one switching device to output the gate pulse signal as the at least one gate clock signal. The clock generator is to generate the at least one gate clock signal in response to the shutdown enable signal, and the at least one switching device is to transmit the gate pulse signal as the at least one gate clock signal in response to the at least one switching signal.

Abstract: A backlight unit includes a DC-DC converter that converts a first voltage to a second voltage in response to a driving pulse signal and a driving controller that outputs the driving pulse signal in response to an over-current control signal to control a reference voltage and a level of the second voltage. The driving controller controls the reference voltage in response to the over-current control signal such that the reference voltage increases prior to the second voltage by a predetermined time when the second voltage needs to be increased. In addition, the driving controller controls the reference voltage in response to the over-current control signal when the second voltage needs to be decreased such that the reference voltage decreases later than the second voltage by the predetermined time.

Abstract: A backlight unit includes a DC-DC converter that converts a first voltage to a second voltage in response to a driving pulse signal and a driving controller that outputs the driving pulse signal in response to an over-current control signal to control a reference voltage and a level of the second voltage. The driving controller controls the reference voltage in response to the over-current control signal such that the reference voltage increases prior to the second voltage by a predetermined time when the second voltage needs to be increased. In addition, the driving controller controls the reference voltage in response to the over-current control signal when the second voltage needs to be decreased such that the reference voltage decreases later than the second voltage by the predetermined time.