Patents by Inventor Yu-Chu Chen

Yu-Chu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240035971
    Abstract: A fluorescence lifetime imaging microscopy system comprises a microscope comprising an excitation source configured to direct an excitation energy to an imaging target, and a detector configured to measure emissions of energy from the imaging target, and a non-transitory computer-readable medium with instructions stored thereon, which perform steps comprising collecting a quantity of measured emissions of energy from the imaging target as measured data, providing a trained neural network configured to calculate fluorescent decay parameters from the quantity of measured emissions of energy, providing the data to the trained neural network, and calculating at least one fluorescence lifetime parameter with the neural network from the measured data, wherein the measured data comprises an input fluorescence decay histogram, and wherein the neural network was trained by a generative adversarial network. A method of training a neural network and a method of acquiring an image are also described.
    Type: Application
    Filed: September 17, 2021
    Publication date: February 1, 2024
    Inventors: Hsin-Chih Yeh, Yuan-I Chen, Yin-Jui Chang, Shih-Chu Liao, Trung Duc Nguyen, Soonwoo Hong, Yu-An Kuo, Hsin-Chin Li
  • Patent number: 11888017
    Abstract: A transparent display panel with a light-transmitting substrate, a plurality of top-emitting micro light emitting diodes, a plurality of bottom-emitting micro light emitting diodes, and a light shielding layer. The light transmissive substrate has a surface. These top-emitting micro light emitting diodes and these bottom-emitting micro light emitting diodes are disposed on the surface of the light transmissive substrate. The bottom-emitting micro light emitting diodes has an epitaxial structure and a light shielding member, the epitaxial structure has a pair of upper and lower surfaces on the opposite sides, the lower surface faces toward the light transmissive substrate, and the light shielding member is disposed on the upper surface to shield the light emitted by the bottom-emitting micro light emitting diodes towards the upper surface.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 30, 2024
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yu-Chu Li, Kuan-Yung Liao, Pei-Hsin Chen, Yi-Ching Chen, Yi-Chun Shih
  • Publication number: 20240021736
    Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 18, 2024
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Wen-Chih CHIANG, Ming-Hong SU, Yung-Han CHEN, Mei-Chen SU, Chia-Ming PAN
  • Patent number: 11855214
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Yu-Yun Peng, Fu-Ting Yen, Ting-Ting Chen, Keng-Chu Lin, Tsu-Hsiu Perng
  • Patent number: 11766465
    Abstract: The present disclosure relates to as external composition for wound healing containing a Lactobacillus fermentation product, which comprises a Lactobacillus fermentation product as an effective component. The Lactobacillus fermentation product is a bacteria-free concentrated filtrate from fermentation of Lactobacillus plantarum and the effective component is loaded onto a pharmaceutically acceptable absorbent carrier or carrying agent. The external composition for wound healing has anti-inflammatory and healing promoting effects on a skin wound after applied directly onto the skin wound.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: September 26, 2023
    Assignee: GRAPE KING BIO LTD
    Inventors: Hsing-Chun Kuo, Chin-Chu Chen, Yen-Lien Chen, Shih-Wei Lin, Yen-Po Chen, Ci-Sian Wang, Yu-Hsin Hou, Yang-Tzu Shih, Ching-Wen Lin, Ya-Jyun Chen, Jia-Lin Jiang, You-Shan Tsai, Zi-He Wu
  • Patent number: 11769837
    Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Ming-Hong Su, Yung-Han Chen, Mei-Chen Su, Chia-Ming Pan
  • Patent number: 11752177
    Abstract: The present invention is related to a method of reducing tobacco addiction in a smoking subject with Lactobacillus fermentum GKF3, including daily administering an oral composition containing the Lactobacillus fermentum GKF3 to the smoking subject, in which the oral composition reduces the total amount of the nicotine metabolites in urine.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: September 12, 2023
    Assignee: GRAPE KING BIO LTD
    Inventors: Chin-Chu Chen, Yen-Lien Chen, Shih-Wei Lin, Yen-Po Chen, Ci-Sian Wang, Yu-Hsin Hou, Yang-Tzu Shih, Ching-Wen Lin, Ya-Jyun Chen, Jia-Lin Jiang, You-Shan Tsai, Zi-He Wu
  • Publication number: 20230253433
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Yu-Chu Lin, Chih Wei Sung, Shih Sian Wang, Chi-Chung Jen, Yu-chien Ku, Yen-Jou Wu, Huai-jen Tung, Po-Zen Chen
  • Patent number: 11640776
    Abstract: An arcuate display device, including an arcuate display surface, a plurality of display units, an image source, and a controller, is provided. The display units are configured on the arcuate display surface in an array manner, and each of the display units includes a plurality of pixels. The controller is configured to receive a plurality of pixel signals from the image source to generate a plurality of frame signals respectively corresponding to the display units. Each of the frame signals includes the pixel signals, a plurality of first dummy signals, and a plurality of second dummy signals, in which the pixel signals respectively correspond to the pixels. A sum of an amount of the pixel signals, an amount of the first dummy signals, and an amount of the second dummy signals in each of the frame signals is same. A driving method of the arcuate display device is also provided.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 2, 2023
    Assignee: AUO Corporation
    Inventors: Yu-Chu Chen, Po Chun Lin, Chun-Hui Huang, Yu-Chi Kang, Yi-Hsiang Hu, Wei-Ting Chen
  • Patent number: 11569833
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: January 31, 2023
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Han Han, Yu-Chu Chen, Wen-Juh Kang
  • Patent number: 11515881
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: November 29, 2022
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chu Chen, Hsin-Han Han, Wen-Juh Kang
  • Publication number: 20220345142
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.
    Type: Application
    Filed: October 8, 2021
    Publication date: October 27, 2022
    Inventors: Hsin-Han HAN, Yu-Chu CHEN, Wen-Juh KANG
  • Publication number: 20220321135
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.
    Type: Application
    Filed: September 15, 2021
    Publication date: October 6, 2022
    Inventors: Yu-Chu CHEN, Hsin-Han HAN, Wen-Juh KANG
  • Publication number: 20220139290
    Abstract: A display device is provided. The display device includes a panel, a memory, and a controller. The panel includes multiple pixels. The memory includes a first section and a second section. The memory stores an aging record table. Multiple brightness attenuation values recorded in the aging table are respectively divided into multiple first portion attenuation values and multiple second portion attenuation values. The first section stores the first portion attenuation values. The second section stores the second portion attenuation values. The controller includes an update circuit and a compensation circuit. The controller is coupled to the panel and the memory. The update circuit receives gray values displayed by the pixels to update the aging table. The compensation circuit reads the first portion attenuation values from the first section so as to perform an aging compensation on the pixels.
    Type: Application
    Filed: July 13, 2021
    Publication date: May 5, 2022
    Applicant: Au Optronics Corporation
    Inventors: Yu-Chi Kang, Yi-Hsiang Hu, Chun-Hui Huang, Wei-Ting Chen, Yu-Chu Chen
  • Patent number: 11322072
    Abstract: A display device is provided. The display device includes a panel, a memory, and a controller. The panel includes multiple pixels. The memory includes a first section and a second section. The memory stores an aging record table. Multiple brightness attenuation values recorded in the aging table are respectively divided into multiple first portion attenuation values and multiple second portion attenuation values. The first section stores the first portion attenuation values. The second section stores the second portion attenuation values. The controller includes an update circuit and a compensation circuit. The controller is coupled to the panel and the memory. The update circuit receives gray values displayed by the pixels to update the aging table. The compensation circuit reads the first portion attenuation values from the first section so as to perform an aging compensation on the pixels.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: May 3, 2022
    Assignee: Au Optronics Corporation
    Inventors: Yu-Chi Kang, Yi-Hsiang Hu, Chun-Hui Huang, Wei-Ting Chen, Yu-Chu Chen
  • Publication number: 20210402738
    Abstract: The present invention provides a sheet having an elastomer layer having a Shore A hardness of less than 40, wherein the elastomer layer has an adhesion force to stainless steel of not more than 11 oz/in at 90 degree peel strength.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Applicants: Nitto Denko Corporation, NITTO, INC.
    Inventors: Derek JORGENSEN, Shinji HOSHINO, Yu-chu CHEN, Masatoshi SUZUKI
  • Patent number: 11075640
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits are configured to convert an input signal according to interleaved clock signals to generate first quantized outputs. The calibration circuit is configured to perform at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit further includes a first adjusting circuit. The first adjusting circuit is configured to analyze adjacent clock signals according to part of the second quantized outputs to generate adjusting information. The skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs and the adjusting information to generate adjustment signals. The adjustment signals are configured to reduce clock skews of the ADC circuits.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: July 27, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. :
    Inventors: Wen-Juh Kang, Yu-Chu Chen, Hsin-Han Han
  • Patent number: 11075641
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines calculating signals, to which the second quantized outputs correspond in a predetermined interval, and averages the calculating signals to generate a reference signal, and compares the reference signal with each of the calculating signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: July 27, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yu-Chu Chen, Ting-Hao Wang
  • Publication number: 20210226644
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines calculating signals, to which the second quantized outputs correspond in a predetermined interval, and averages the calculating signals to generate a reference signal, and compares the reference signal with each of the calculating signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.
    Type: Application
    Filed: September 24, 2020
    Publication date: July 22, 2021
    Inventors: Wen-Juh KANG, Yu-Chu CHEN, Ting-Hao WANG
  • Patent number: 11070221
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines maximum value signals, to which the second quantized outputs correspond in a predetermined interval, and averages the maximum value signals to generate a reference signal, and compares the reference signal with each of the maximum value signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: July 20, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.
    Inventors: Ting-Hao Wang, Hsin-Han Han, Yu-Chu Chen