Abstract: A serial peripheral interface memory module using address cache comprises a flash memory array for storing data, a serial/parallel convertor for receiving serial signals and generating a control command, an address and data, an address register, an address accumulator for accumulating the address in the address register and storing the accumulated address back to the address register, and a flash memory controller for controlling the access to the flash memory array. When the control command is a standard command, the serial/parallel controller first stores the address following the control command into the address register and then the flash memory controller accesses data according to the address in the address register. When the control command is a specific command, the flash memory controller directly accesses data according to the address in the address register without waiting for an address update.

Abstract: A serial transmission controller, a serial transmission decoder and a serial transmission method thereof are disclosed. First, a current address and an access address are compared to select one of a plurality of transmission address modes as an access address mode and then to produce corresponding address information. The transmission address modes use different bits to transmit the address information respectively. According to the access address mode, an access command is selected from a serial command set. Finally, the access command and the address information are transmitted to a serial interface serially. After the access command is encoded to different length of bits, the encoded access command is transmitted to the serial interface so as to reduce the transmission bits and improve the transmission efficiency.

Abstract: An optical storage system for coupling to at least a plurality of peripheral devices. The optical storage system includes a data read subsystem to read out data stored in an optical storage medium, a data process subsystem to generate address information and data information according to the read out data, and an interface controller to generate output data according to the address information and the data information and to transfer the output data to one of the peripheral devices. A number of bits of the output data being transferred in parallel is configurable according to a parallel bit number. The data information and the address information are transferred via the same pins.

Abstract: A serial peripheral interface memory module using address cache comprises a flash memory array for storing data, a serial/parallel convertor for receiving serial signals and generating a control command, an address and data, an address register, an address accumulator for accumulating the address in the address register and storing the accumulated address back to the address register, and a flash memory controller for controlling the access to the flash memory array. When the control command is a standard command, the serial/parallel controller first stores the address following the control command into the address register and then the flash memory controller accesses data according to the address in the address register. When the control command is a specific command, the flash memory controller directly accesses data according to the address in the address register without waiting for an address update.

Abstract: A RF microwave connector for telecommunication has a central terminal with a guiding groove and a fixing groove. The diameter of the cross section of the guiding groove is larger than the diameter of an inner wire of a coaxial cable and the diameter of the cross section of the upper end of the fixing groove is smaller than the diameter of the inner wire. The inner wire is thrust in the fixing groove by the walls of the fixing groove to cause the combination of the central terminal and the inner wire to be more stable and the connector to have better signal transmission quality by thrusting the inner wire into the fixing groove.

Abstract: A serial transmission controller, a serial transmission decoder and a serial transmission method thereof are disclosed. First, a current address and an access address are compared to select one of a plurality of transmission address modes as an access address mode and then to produce corresponding address information. The transmission address modes use different bits to transmit the address information respectively. According to the access address mode, an access command is selected from a serial command set. Finally, the access command and the address information are transmitted to a serial interface serially. After the access command is encoded to different length of bits, the encoded access command is transmitted to the serial interface so as to reduce the transmission bits and improve the transmission efficiency.

Abstract: A RF microwave connector for telecommunication has a central terminal with a guiding groove and a fixing groove. The diameter of the cross section of the guiding groove is larger than the diameter of an inner wire of a coaxial cable and the diameter of the cross section of the upper end of the fixing groove is smaller than the diameter of the inner wire. The inner wire is thrust in the fixing groove by the walls of the fixing groove to cause the combination of the central terminal and the inner wire to be more stable and the connector to have better signal transmission quality by thrusting the inner wire into the fixing groove.

Abstract: A slave and a master of serial peripheral interface, system thereof and method thereof are provided. The invention saves the read address during the process of data-read in the serial peripheral interface (SPI) and adds a new data-read command so that when the former data address is followed by the next one, the transmission of the read address is ignored by using new read command in order to increase the efficiency of data read in the serial peripheral interface.

Abstract: A method and apparatus for avoiding bi-directional signal fighting of a serial interface is disclosed. The serial peripheral interface includes a clock signal line and a data line. In this method, during normal operation, a first clock signal is received and transformed to output a second clock signal in the clock signal line, wherein the second clock signal has a first duty period. When the output of the data in the data line switches to input, the second clock signal switches to have the second duty period, wherein the second duty period is larger than the first duty period.

Abstract: A slave and a master of serial peripheral interface, system thereof and method thereof are provided. The invention saves the read address during the process of data-read in the serial peripheral interface (SPI) and adds a new data-read command so that when the former data address is followed by the next one, the transmission of the read address is ignored by using new read command in order to increase the efficiency of data read in the serial peripheral interface.

Abstract: The present invention provides a memory device with the serial transmission interface and an error correction method for the serial transmission interface. The memory device comprises an error correction mechanism to detect or automatically correct the error earlier to make sure the correctness of the data transmission while the serial transmission interface accesses the memory. Further, the action of error corrections and data re-transmissions performed by the master device can be reduced.

Abstract: An optical storage system for coupling to at least a plurality of peripheral devices. The optical storage system includes a data read subsystem to read out data stored in an optical storage medium, a data process subsystem to generate address information and data information according to the read out data, and an interface controller to generate output data according to the address information and the data information and to transfer the output data to one of the peripheral devices. A number of bits of the output data being transferred in parallel is configurable according to a parallel bit number. The data information and the address information are transferred via the same pins.

Abstract: A method and apparatus for avoiding bi-directional signal fighting of a serial interface is disclosed. The serial peripheral interface includes a clock signal line and a data line. In this method, during normal operation, a first clock signal is received and transformed to output a second clock signal in the clock signal line, wherein the second clock signal has a first duty period. When the output of the data in the data line switches to input, the second clock signal switches to have the second duty period, wherein the second duty period is larger than the first duty period.