Patents by Inventor Yu-Chuan Liao

Yu-Chuan Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12317573
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: May 27, 2025
    Assignee: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Patent number: 12114547
    Abstract: Provided is a display panel, including a substrate, multiple pixel circuits, an insulating layer, multiple first electrodes, a first isolation structure, and a second isolation structure. The pixel circuits are located on the substrate. The insulating layer is located on the pixel circuits and has multiple through holes. The first electrodes are located on the insulating layer and are respectively electrically connected to the pixel circuits through the through holes. The first isolation structure is located on the insulating layer and overlaps the through holes. The second isolation structure includes multiple separating parts and multiple cover parts. The separating parts and the first isolation structure at least partially overlap, and the cover parts respectively overlap the through holes and the first isolation structure.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: October 8, 2024
    Assignee: Au Optronics Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20240234535
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: July 11, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20240136420
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: April 25, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20220367591
    Abstract: Provided is a display panel, including a substrate, multiple pixel circuits, an insulating layer, multiple first electrodes, a first isolation structure, and a second isolation structure. The pixel circuits are located on the substrate. The insulating layer is located on the pixel circuits and has multiple through holes. The first electrodes are located on the insulating layer and are respectively electrically connected to the pixel circuits through the through holes. The first isolation structure is located on the insulating layer and overlaps the through holes. The second isolation structure includes multiple separating parts and multiple cover parts. The separating parts and the first isolation structure at least partially overlap, and the cover parts respectively overlap the through holes and the first isolation structure.
    Type: Application
    Filed: November 5, 2021
    Publication date: November 17, 2022
    Applicant: Au Optronics Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun