Patents by Inventor Yu-Chuan Lin

Yu-Chuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200298218
    Abstract: A method of using biopolymer to synthesize titanium-containing silicon oxide material and applications thereof are disclosed. The method comprises steps: mixing a titanium source, a silicon source, an acid source, a base source, a biopolymer and a solvent to form an aqueous solution, and letting the aqueous solution react to form a semi-product; performing aging, solid-liquid separation and drying of the semi-product to obtain a dried solid; and performing calcination or extraction of the dried solid to obtain a titanium-containing silicon oxide material with a high specific surface area. The present invention adopts a biopolymer as the templating agent, which makes the fabrication process of titanium-containing silicon oxide material more environment-friendly. After calcination or extraction, the product still has superior catalytic activity, able to catalyze epoxidation of olefins and favorable for the production of epoxide.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Yu-Chuan HSU, Pin-Hsuan HUANG, Chien-Chang CHIANG, Ying-Shih CHANG, Hsi-Chin TSAI, Hong-Ping LIN
  • Patent number: 10780431
    Abstract: A method of using biopolymer to synthesize titanium-containing silicon oxide material and applications thereof are disclosed. The method comprises steps: mixing a titanium source, a silicon source, an acid source, a base source, a biopolymer and a solvent to form an aqueous solution, and letting the aqueous solution react to form a semi-product; performing aging, solid-liquid separation and drying of the semi-product to obtain a dried solid; and performing calcination or extraction of the dried solid to obtain a titanium-containing silicon oxide material with a high specific surface area. The present invention adopts a biopolymer as the templating agent, which makes the fabrication process of titanium-containing silicon oxide material more environment-friendly. After calcination or extraction, the product still has superior catalytic activity, able to catalyze epoxidation of olefins and favorable for the production of epoxide.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 22, 2020
    Assignee: ORIENTAL UNION CHEMICAL CORP.
    Inventors: Yu-Chuan Hsu, Pin-Hsuan Huang, Chien-Chang Chiang, Ying-Shih Chang, Hsi-Chin Tsai, Hong-Ping Lin
  • Publication number: 20200273748
    Abstract: A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure and over the source/drain region, removing a portion of the source/drain contact such that a hole is formed in the ILD structure and over a remaining portion of the source/drain contact, forming a hole liner lining a sidewall of the hole after removing the portion of the source/drain contact, and forming a conductive structure in the hole.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao CHANG, Jia-Chuan YOU, Yu-Ming LIN, Chih-Hao WANG, Wai-Yi LIEN
  • Patent number: 10755977
    Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate, a gate stack, a gate spacer, a conductive feature, and a conductive cap. The substrate has a source/drain region. The gate stack is on the substrate. The gate spacer is alongside the gate stack. The conductive feature is on the source/drain region. The conductive cap is on the conductive feature and has a top in a position lower than a top of the gate spacer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Chia-Hao Chang, Wei-Hao Wu, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 10744493
    Abstract: A method of using biopolymer to synthesize titanium-containing silicon oxide material and applications includes mixing a titanium source, a silicon source, an acid source, a base source, a biopolymer and a solvent to form an aqueous solution, and letting the aqueous solution react to form a semi-product; performing aging, solid-liquid separation and drying of the semi-product to obtain a dried solid; and performing calcination or extraction of the dried solid to obtain a titanium-containing silicon oxide material with a high specific surface area. The present invention adopts a biopolymer as the templating agent, which makes the fabrication process of titanium-containing silicon oxide material more environment-friendly. After calcination or extraction, the product still has superior catalytic activity, able to catalyze epoxidation of olefins and favorable for the production of epoxide.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 18, 2020
    Assignee: Oriental Union Chemical Corp.
    Inventors: Yu-Chuan Hsu, Pin-Hsuan Huang, Chien-Chang Chiang, Ying-Shih Chang, Hsi-Chin Tsai, Hong-Ping Lin
  • Patent number: 10742360
    Abstract: Techniques and examples of layer mapping, channel state information (CSI) feedback and hybrid automatic repeat request (HARQ) feedback in mobile communications are described. A user equipment (UE) receives from a base station one or more reference signals, which may be non-zero power (NZP) or zero power (ZP), on one or more time-frequency resources indicated by a network via a communication link between the UE and the base station. The UE estimates, based on the receiving, a subspace spanned by a channel response of an interfering signal. The UE determines a precoding matrix indicator (PMI) based on the estimated subspace. The UE transmits to the base station a channel state information (CSI) feedback comprising at least the PMI. The PMI may include at least a first precoder and a second precoder.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: August 11, 2020
    Assignee: MediaTek Inc.
    Inventors: Weidong Yang, Lung-Sheng Tsai, Tzu-Han Chou, Yu-Chuan Lin, Bo-Si Chen
  • Patent number: 10720514
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor fin, a first gate stack, and a first metal element-containing dielectric mask. The semiconductor fin protrudes from the substrate. The first gate stack is over the semiconductor fin. The first metal element-containing dielectric mask is over the first gate stack.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Wang, Wai-Yi Lien, Gwan-Sin Chang, Yu-Ming Lin, Ching Hsueh, Jia-Chuan You, Chia-Hao Chang
  • Patent number: 10720910
    Abstract: An eye diagram observation device is provided. The eye diagram observation device includes an eye diagram determination circuit and a clock generator. The eye diagram determination circuit obtains an eye diagram corresponding to an input signal pair based on a delayed sampling clock. The clock generator includes a voltage to time converter (VTC). The VTC generates a delayed clock based on a voltage value of an input voltage. The clock generator generates the delayed sampling clock based on the delayed clock. The eye diagram observation device may reduce power consumption and a layout area via the VTC.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 21, 2020
    Assignee: ASMedia Technology Inc.
    Inventor: Yu-Chuan Lin
  • Publication number: 20200218562
    Abstract: The present disclosure provides a communication method for virtual machines, an electronic device, and a non-transitory computer readable storage medium. The communication method for virtual machines suitable for a virtual machine architecture comprises the steps of: transmitting, through a shared link, an interrupt instruction to a second virtual machine by a first virtual machine; reading, in a shared configuration database, an instruction data corresponding to the interrupt instruction by the second virtual machine; and executing the instruction data and transmitting a result data through a virtual control plane to the first virtual machine by the second virtual machine, to exchange the data between the first virtual machine and the second virtual machine through the virtual control plane.
    Type: Application
    Filed: August 20, 2019
    Publication date: July 9, 2020
    Inventors: Wei-Chuan WANG, Po-Kai CHUANG, Yu-Ting TING, Chien-Kai TSENG, Tse HO LIN
  • Patent number: 10698261
    Abstract: A backlight module having a bearing plate and a light module is provided. The bearing plate has a bearing surface, which includes a trough, a first groove, a first inner stage, and a first outer stage. The first groove is disposed close to the trough. The first inner stage is between the trough and the first groove while the first outer stage is on the side of the first groove opposite to the first inner stage. The light module is disposed on the bearing surface and corresponds to the trough. Comparing to the first inner stage, the first outer stage is more protruding toward the light module.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 30, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Chung Huang, Yu-Chuan Lin
  • Publication number: 20200194438
    Abstract: A method of forming an apparatus comprises forming filled trenches within a semiconductive structure having a well region comprising one or more dopants, the filled trenches extending into the well region and each individually comprising a conductive gate structure and a dielectric liner intervening between the conductive gate structure and the semiconductive structure. A fluorine-doped region is formed at junctions between the well region and additional regions of the semiconductive structure overlying the well region. The additional regions of the semiconductive structure are doped with one or more additional dopants having a different conductivity type than that of the one or more dopants of the well region after forming the fluorine-doped region. The semiconductive structure is annealed after doping the additional regions thereof. Apparatuses, memory devices, and electronic systems also described.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Inventors: Oscar O. Enomoto, Chin Chuan Liu, Chia Wei Tsai, Yu Jen Lin
  • Publication number: 20200183233
    Abstract: A backlight module having a bearing plate and a light module is provided. The bearing plate has a bearing surface, which includes a trough, a first groove, a first inner stage, and a first outer stage. The first groove is disposed close to the trough. The first inner stage is between the trough and the first groove while the first outer stage is on the side of the first groove opposite to the first inner stage. The light module is disposed on the bearing surface and corresponds to the trough. Comparing to the first inner stage, the first outer stage is more protruding toward the light module.
    Type: Application
    Filed: June 28, 2019
    Publication date: June 11, 2020
    Inventors: Chih-Chung Huang, Yu-Chuan Lin
  • Publication number: 20200161439
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.
    Type: Application
    Filed: May 8, 2019
    Publication date: May 21, 2020
    Inventors: Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20200158122
    Abstract: A ventilation system comprises a ventilation fan with a lamp for installing to a ceiling having an installation opening. The ventilation fan comprises a housing, a fan module, a power box, a junction box and a lamp module. The housing has a first opening and an air outlet. The fan module disposed in the housing and comprises an inlet opening and an outlet opening. The outlet opening communicates with the air outlet. Three accommodation spaces are formed between the housing and the fan module at different corners of the housing and disposed away from the air outlet. The power box and the junction box disposed at two of the accommodation spaces. The power box has a first circuit board. The lamp module and the housing are located at opposite sides of the installation opening. The junction box is electrically connected to the first circuit board and the lamp module.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Inventors: YU-HSIANG HUANG, YUAN-CHUAN LIU, CHIH-HUA LIN
  • Publication number: 20200152583
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien MA, Haw-Chuan WU, Shih-Hao TSAI, Yu-Chuan LIN
  • Patent number: 10651085
    Abstract: A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure and over the source/drain region, removing a portion of the source/drain contact such that a hole is formed in the ILD structure and over a remaining portion of the source/drain contact, forming a hole liner lining a sidewall of the hole, and forming a conductive structure in the hole.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Chang, Jia-Chuan You, Yu-Ming Lin, Chih-Hao Wang, Wai-Yi Lien
  • Patent number: 10648940
    Abstract: An electrochemical biosensor includes a substrate, a plurality of layered active metal parts, a plurality of layered electrodes, a reaction confinement layer, an electrochemical reactive layer and a cover piece. The substrate is formed with through holes each of which is defined by an interior wall surface and penetrates top and bottom surfaces. Each of the layered active metal parts is formed at least upon a respective one of the interior wall surfaces. The layered electrodes are formed on the layered active metal parts. The reaction confinement layer confines a reactor space over a region where the through holes are formed. The electrochemical reactive layer is disposed in the reactor space and is electrically coupled to the layered electrodes.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: May 12, 2020
    Assignee: Taiwan Green Point Enterprises Co., Ltd.
    Inventors: Yu-Chuan Lin, Sung-Yi Yang, Yi-Cheng Lin
  • Publication number: 20200144105
    Abstract: A method includes forming a dummy gate stack over a substrate; forming a gate spacer on a sidewall of the dummy gate stack; after forming the gate spacer, forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region and adjacent to the gate spacer; replacing the dummy gate stack with a metal gate stack; forming a protective layer over the metal gate stack and the gate spacer; after forming the protective layer, removing the first interlayer dielectric layer to expose a sidewall of the gate spacer and a sidewall of the protective layer; and forming a bottom conductive feature over the source/drain region.
    Type: Application
    Filed: December 30, 2019
    Publication date: May 7, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Wai-Yi LIEN, Yu-Ming LIN
  • Publication number: 20200135858
    Abstract: The present disclosure provides a method for semiconductor fabrication. The method includes epitaxially growing source/drain feature on a fin; forming a silicide layer over the epitaxial source/drain feature; forming a seed metal layer on the silicide layer; forming a contact metal layer over the seed metal layer using a bottom-up growth approach; and depositing a fill metal layer over the contact metal layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: April 30, 2020
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Jia-Chuan You, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20200133070
    Abstract: A light source module includes a light guide plate, a light source and a light regulating element. The light guide plate has a first light emitting surface and a second light emitting surface, and a light incident surface connected between the first light emitting surface and the second light emitting surface. The second light emitting surface has a plurality of microstructures. The light source is disposed adjacent to the light incident surface. The light regulating element is disposed adjacent to the second light emitting surface. A dual display device including the light source module, a first display panel and a second display panel is also provided. The first display panel is disposed on a side of the light guide plate facing the first light emitting surface. The second display panel is disposed on a side of the light regulating element that is away from the light guide plate.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 30, 2020
    Inventors: Hui-Chuan CHEN, Wen-Chin TSAI, Chung-Yang FANG, Yin-Jen LIN, Yu-Fan CHEN