Patents by Inventor Yu-Chun Ho
Yu-Chun Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240124706Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, and a fourth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), and the fourth repeating unit has a structure of Formula (IV), a structure of Formula (V) or a structure of Formula (VI) wherein A1, A2, A3, Z1, R1, R2, R3 and Q are as defined in the specification.Type: ApplicationFiled: September 22, 2023Publication date: April 18, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Lin CHU, Jen-Chun CHIU, Po- Hsien HO, Yu-Min HAN, Meng-Hsin CHEN, Chih-Hsiang LIN
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Patent number: 11942750Abstract: A laser inspection system is provided. A laser source emits a laser with a first spectrum and the laser is transmitted by a first optical fiber. A gain optical fiber doped with special ions is connected to the first optical fiber, and a light detector is provided around the gain optical fiber. When the laser with the first spectrum passes through the gain optical fiber, the gain optical fiber absorbs part of the energy level of the laser with the first spectrum, so that the laser with the first spectrum is converted to generate light with a second spectrum based on the frequency conversion phenomenon. The light detector detects the intensity of the light with the second spectrum, so that the power of the laser source can be obtained.Type: GrantFiled: November 23, 2020Date of Patent: March 26, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Chi Lee, Hsin-Chia Su, Shih-Ting Lin, Yu-Cheng Song, Fu-Shun Ho, Chih-Chun Chen
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Patent number: 10431465Abstract: A method of fabricating a semiconductor structure includes providing a semiconductor substrate, forming a trench in the semiconductor substrate, overfilling the trench with a first semiconductor material, wherein the first semiconductor material does not have a dopant, forming a second semiconductor material on the first semiconductor material, wherein the second semiconductor material contains a dopant, and performing a thermal treatment so that the dopant in the second semiconductor material diffuses into the first semiconductor material to form a doped third semiconductor material in the trench.Type: GrantFiled: September 18, 2017Date of Patent: October 1, 2019Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Ming Kao, Rong-Gen Wu, Han-Wen Chang, Chun-Hsu Chen, Yu-Chun Ho
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Publication number: 20190088484Abstract: A method of fabricating a semiconductor structure includes providing a semiconductor substrate, forming a trench in the semiconductor substrate, overfilling the trench with a first semiconductor material, wherein the first semiconductor material does not have a dopant, forming a second semiconductor material on the first semiconductor material, wherein the second semiconductor material contains a dopant, and performing a thermal treatment so that the dopant in the second semiconductor material diffuses into the first semiconductor material to form a doped third semiconductor material in the trench.Type: ApplicationFiled: September 18, 2017Publication date: March 21, 2019Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Ming KAO, Rong-Gen WU, Han-Wen CHANG, Chun-Hsu CHEN, Yu-Chun HO
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Publication number: 20020076934Abstract: A method of removaling photoresistance is disclosed: first, unqualified pattern on the substrate is taken away by a plasma process under a mixture of oxygen and fluorocarbon gases. Thereafter, the polymer, which is produced by reaction between the plasma and photoresist, is removed by organic solvent (ACT690/NMP). When the plasma process is applied, the plasma process also could over-etch in the silicon-oxy-nitride layer and the polymer is entirely taken off in the plasma process. Silicon-oxy-nitride is then deposited to complement the loss part in the plasma process. After that, lithography process repeats again to form a new pattern. Finally, ADI is performed to make sure if the new pattern is in the acceptable range of the process. Next, metal layer and silicon-oxy-nitride layer are patterned by the new pattern to form the interconnect.Type: ApplicationFiled: December 15, 2000Publication date: June 20, 2002Inventors: Chun-Chieh Fang, Po-Sheng Hu, Yu-Chun Ho
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Patent number: 6184081Abstract: A process for fabricating a DRAM capacitor structure, in which the capacitor upper plate structure is defined during the formation of bit line contact hole opening, and substrate contact hole opening procedure, eliminating the need for a specific upper plate, photolithographic masking procedure, has been developed. The process features isolating a polysilicon upper plate structure, during an isotropic RIE cycle, also creating an undercut polysilicon region, in the contact holes, which are opened simultaneously during the upper plate definition. Subsequent silicon nitride spacers, on the sides of the contact holes, provides insulation between the polysilicon upper plate structure, and bit line, and substrate contact plug structures, now located in the contact holes. The undercut polysilicon regions, allow the formation of thicker silicon nitride spacers, to be formed in this undercut region.Type: GrantFiled: October 8, 1999Date of Patent: February 6, 2001Assignee: Vanguard International Semiconductor CorporationInventors: Erik S. Jeng, Bi-Ling Chen, Wei-Ray Lin, Yu-Chun Ho, Ming-Hong Kuo
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Patent number: 5990018Abstract: The present invention is a method for improviding an oxide etching process by using a nitrogen-based plasma. An additional nitrogen-based plasma step is used to inhibit or delay the formation of observed residual bubbles during a dry etching process. The method comprises the steps of etching the oxide layer by reactive ion etching and immersing the oxide layer in a nitrogen plasma.Type: GrantFiled: September 11, 1996Date of Patent: November 23, 1999Assignee: Vanguard International Semiconductor CorporationInventors: Yu-Chun Ho, Tzu-Shih Yen, Hung-Yi Luo
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Patent number: 5932115Abstract: The present invention is a method of manufacturing crown shape capacitors for use in DRAM semiconductor memory. The method includes the steps of forming a first polysilicon layer, patterning a photoresist on the first polysilicon layer, etching the first polysilicon layer, using oxygen plasma to strip the photoresist, forming a side wall polymer onto the side walls of the first polysilicon layer, using the side wall polymer as a mask to etch back the first polysilicon layer to form a crown shape structure, removing the side wall polymer, depositing a dielectric layer onto the first polysilicon layer, and depositing a second polysilicon layer onto the dielectric layer.Type: GrantFiled: May 3, 1996Date of Patent: August 3, 1999Assignee: Vanguard International Semiconductor CorporationInventors: Yu-Chun Ho, Meng-Chao Cheng, Pei-Wen Li, Hsu-Li Cheng, Yu-Hua Huang, Shing-Huang Wu
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Patent number: 5851877Abstract: An etching process is used to etch the polysilicon layer. Then, Polymers are formed on the polysilicon layer after an ash step is performed. An organic layer is formed on the surface of the polysilicon layer, and on the polymers. An anisotropically etch is carried out to etch the organic layer, thereby forming organic side wall spacers on the side walls of the polysilicon layer. The etching is continuously performed to etch the polysilicon layer using the polymers and organic side wall spacers as masks. Next, an ash and a RCA clean procedure are performed to remove the residual polymers and the organic layer. A dielectric layer is then deposited on the surface of the polysilicon. A conductive layer is deposited over the dielectric layer.Type: GrantFiled: January 6, 1998Date of Patent: December 22, 1998Assignee: Vanguard International Semiconductor CorporationInventors: Yu-Chun Ho, Hsiang-Wei Tseng
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Patent number: 5804489Abstract: The present invention is a method of manufacturing crown shape capacitors in the semiconducter memories. Using a single step etching to farbricate the capacitor in a DRAM cell. The method can form side wall polymers and etching byproductions on the surface of the first polysilicon, using the side wall polymers and the etching byproductions as a mask to form the crown shape capacitors with pillars. Moreover, this present invention can form the crown shape structure and pillars in the same step, the crown shape structure and the pillars increase the surface area of the capacitor. Therefore the present invention will increase the performance of the capacitor.Type: GrantFiled: July 12, 1996Date of Patent: September 8, 1998Assignee: Vanguard International Semiconductor CorporationInventors: Fu-Liang Yang, Erik S. Jeng, Yu-Chun Ho, Bin Liu, Chao-Ming Koh