Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: A wafer container includes a frame, a door and at least a pair of shelves. The frame has opposite sidewalls. The pair of the shelves are respectively disposed and aligned on the opposite sidewalls of the frame. Various methods and devices are provided for holding at least one wafer to the shelves during transport.

Abstract: A semiconductor wafer processing system includes a stocker having an interior surface, a wafer carrier disposed within the stocker, a wafer shelf disposed within the wafer carrier for storing a semiconductor wafer, and a discharge circuit including a first conductor electrically coupled to the wafer shelf and a first current controller electrically coupled to the first conductor and to the interior surface of the stocker.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: A semiconductor wafer processing system includes a stocker having an interior surface, a wafer carrier disposed within the stocker, a wafer shelf disposed within the wafer carrier for storing a semiconductor wafer, and a discharge circuit including a first conductor electrically coupled to the wafer shelf and a first current controller electrically coupled to the first conductor and to the interior surface of the stocker.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: A multiple-piece vacuum-insulated heating tank for use in a water dispenser includes a threaded cover, a thermal insulation cover, and a heating tank body. The threaded cover is mounted on an upper opening of the heating tank body and includes a plastic cover and a protective cover mounted on and around the plastic cover. The thermal insulation cover is fitted in the upper opening and includes an upper cover and a lower cover. The lower cover is cup-shaped; is mounted with a heating tube, a water inlet pipe, a water outlet pipe, a thermowell, a temperature-sensing heat pipe, a heat collector block, and two snap-action thermostats at the bottom side; and has a sidewall formed with a step adjacent to the bottom side. The heating tank not only has a multiple-piece structure that facilitates mass production and maintenance, but also dispenses with electronic temperature control as is conventionally required.

Abstract: A multiple-piece vacuum-insulated heating tank for use in a water dispenser includes a threaded cover, a thermal insulation cover, and a heating tank body. The threaded cover is mounted on an upper opening of the heating tank body and includes a plastic cover and a protective cover mounted on and around the plastic cover. The thermal insulation cover is fitted in the upper opening and includes an upper cover and a lower cover. The lower cover is cup-shaped; is mounted with a heating tube, a water inlet pipe, a water outlet pipe, a thermowell, a temperature-sensing heat pipe, a heat collector block, and two snap-action thermostats at the bottom side; and has a sidewall formed with a step adjacent to the bottom side. The heating tank not only has a multiple-piece structure that facilitates mass production and maintenance, but also dispenses with electronic temperature control as is conventionally required.

Abstract: The present invention discloses a push-type anti-scalding water dispenser faucet having: a faucet main body; a valve core assembly controlling a water output; a press board mechanism driving the valve core assembly to move; a retaining structure allowing the press board mechanism to switch between a locking position and a release position. The water dispenser faucet comprises a disposable finger stall for mounting onto the press board mechanism or a finger of a user.

Abstract: An ink is provided, which includes a resin, UV curable monomer, and photo initiator. The resin is formed by reacting a plurality of end capping agents with a dendrimer compound in an environment including esterification catalyst, inhibitor, and first solvent. The dendrimer compound is formed by reacting a multi-hydroxy compound and a plurality of hydroxy-containing epoxy compounds in an environment including alkaline catalyst and second solvent. The multi-hydroxy compound and the hydroxy-containing epoxy compounds have a molar ratio of 1:6 to 1:20, and the multi-hydroxy compound and the end capping agents have a molar ratio of 1:6 to 1:20. The end capping agents include acrylic acid, methacrylic acid, glycidyl methacrylate, or 2-amino acrylic acid. The resin and the UV curable monomer have a weight ratio of 100:30 to 100:5000, and the resin and the photo initiator have a weight ratio of 100:30 to 100:500.

Abstract: An ink is provided, which includes a resin, UV curable monomer, and photo initiator. The resin is formed by reacting a plurality of end capping agents with a dendrimer compound in an environment including esterification catalyst, inhibitor, and first solvent. The dendrimer compound is formed by reacting a multi-hydroxy compound and a plurality of hydroxy-containing epoxy compounds in an environment including alkaline catalyst and second solvent. The multi-hydroxy compound and the hydroxy-containing epoxy compounds have a molar ratio of 1:6 to 1:20, and the multi-hydroxy compound and the end capping agents have a molar ratio of 1:6 to 1:20. The end capping agents include acrylic acid, methacrylic acid, glycidyl methacrylate, or 2-amino acrylic acid. The resin and the UV curable monomer have a weight ratio of 100:30 to 100:5000, and the resin and the photo initiator have a weight ratio of 100:30 to 100:500.