Patents by Inventor Yu Chung

Yu Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240193984
    Abstract: Provided is a full-screen display device with unit pixel having function for emitting and receiving light, including a water-oxygen barrier layer, a protective panel, a plurality of unit pixels, a light-shielding layer, and a plurality of lens. At least one of the unit pixels has a light-emitting area inside, and has a light-sensing area inside or outside. For biometrics recognition, the light-emitting area emits an incident light, which penetrates through the water-oxygen barrier layer and scatters outwardly by at least one of the lenses. The scattered incident light penetrates through the protective panel, and reflected by a test object. The reflected light penetrates through the protective panel and is converged by at least one of the lenses. The converged reflected light penetrates through the water-oxygen barrier, and the light-sensing area receives and converts the reflected light to an image electrical signal.
    Type: Application
    Filed: November 6, 2023
    Publication date: June 13, 2024
    Inventors: Chun-Yu Lee, Jun-Wen Chung
  • Publication number: 20240194279
    Abstract: A system can include a plurality of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices, to perform operations comprising: determining whether a parameter of a power supply of the volatile memory device satisfies a threshold criterion; responsive to determining that the parameter of the power supply satisfies the threshold criterion, modifying a value of a parameter of a program operation; and programming, using the modified value of the parameter, designated data stored on the volatile memory device to a designated location on the non-volatile memory device.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 13, 2024
    Inventors: Tomer Tzvi Eliash, Yu-Chung Lien
  • Publication number: 20240194128
    Abstract: Provided is a full-screen display device having different unit pixels for emitting and receiving light, including a water-oxygen barrier layer, a protective panel, a plurality of unit pixels, a light-shielding layer, and a plurality of lenses. When the device performs biometric recognition, at least one unit pixel is defined as a light-emitting element, at least one unit pixel is defined as a sensing element, and the sensing element has a light-sensing area. The light-emitting element emits an incident light to penetrate the water-oxygen barrier layer and scatter outwardly by at least one lens. The scattered incident light penetrates the protective panel, and then reflected by a test object, followed by penetrating the protective panel, and entering at least one lens, which converges the reflected light. The converged light penetrates the water-oxygen barrier layer to be received by the light-sensing area and converted into an image electrical signal.
    Type: Application
    Filed: October 25, 2023
    Publication date: June 13, 2024
    Inventors: Chun-Yu Lee, Jun-Wen Chung
  • Publication number: 20240190013
    Abstract: A method of providing a food intake support service includes outputting, by a second device included in a robot device comprising the second device and a first device, an alarm when a preset food intake time arrives, receiving, by the second device, a plurality of sensing data related to food intake from the first device, analyzing, by the second device, the plurality of sensing data; outputting, by the second device, feedback based on the plurality of sensing data and performing, by the second device, a real-time interactive communication based on inputted voice data.
    Type: Application
    Filed: February 16, 2024
    Publication date: June 13, 2024
    Inventors: Jihee KIM, Se Jin CHUNG, Kwang Yu KIM, Tae Yang OH, Dong Myoung WOO
  • Patent number: 12008239
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: June 11, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
  • Patent number: 12009293
    Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Cheng-Ting Chung, Wei Ju Lee
  • Publication number: 20240185935
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells in the block using a first bitline voltage applied during a program verify phase, wherein the first bitline voltage is higher than a default program verify bitline voltage.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Chung Lien, Zhenming Zhou
  • Publication number: 20240185924
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells associated with a wordline in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells associated with the wordline in the block using a first pass voltage applied during a program verify phase, wherein the first pass voltage is lower than a default program verify pass voltage.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Chung Lien, Zhenming Zhou
  • Publication number: 20240184449
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.
    Type: Application
    Filed: January 9, 2023
    Publication date: June 6, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
  • Publication number: 20240185934
    Abstract: A request to perform a program operation to program a set of memory cells on a memory device comprising a sense amplifier circuit is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A modified sensing time period, exceeding a default sensing time period, is determined based on the defect indicator. The program operation is performed using the modified sensing time period during a program verify phase of the program operation.
    Type: Application
    Filed: November 28, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Chung Lien, Zhenming Zhou
  • Publication number: 20240185931
    Abstract: A request to perform a program operation to program a set of memory cells on a memory device is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A value of a program verify parameter is determined based on the defect indicator. The program operation is performed using the value of the program verify parameter during a program verify phase of the program operation.
    Type: Application
    Filed: November 28, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Chung Lien, Jun Wan, Zhenming Zhou
  • Publication number: 20240176508
    Abstract: A system with a memory device and a processing device operatively coupled with the memory device, to perform operations including identifying a lifecycle state associated with a segment of the memory device, selecting, based on the lifecycle state, an erase policy for performing an erase operation with respect to the segment, and causing the erase operation to be performed with respect to the segment in accordance with the erase policy.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Inventors: Yu-Chung Lien, Zhongguang Xu, Ronit Roneel Prakash, Zhenming Zhou
  • Publication number: 20240177781
    Abstract: A method for partial block read compensation can include receiving a read request that specifies a memory cell connected to a string of series-connected memory cells in an array of memory cells on a memory device, the string located at an intersection of a wordline and a bitline, and causing a first voltage applied to the wordline to which the specified memory cell is connected to ramp to a first predetermined value. The method can include causing a second voltage applied to the bitline to which the specified memory cell is connected to ramp to a second predetermined value, and can include comparing, using a current comparator, a current along the string with a reference current to generate an analog output signal. It can also include causing a voltage offset, based on the analog output signal, to be applied to a read voltage level during a sensing operation.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 30, 2024
    Inventors: Yu-Chung Lien, Jun Wan, Zhenming Zhou
  • Publication number: 20240178631
    Abstract: A laser diode includes an original substrate having a substrate coefficient of thermal expansion, an epitaxy structure formed on the original substrate, and a composite multi-layer metal board disposed below the original substrate and at least including a first metal layer and a second metal layer. The first metal layer and the second metal layer are stacked, a material of the first metal layer is different from a material of the second metal layer, and the composite multi-layer metal board has a modified coefficient of thermal expansion. The original substrate has an initial thickness as the epitaxy structure is grown thereon, the original substrate is thinned to a combining thickness for attaching the composite multi-layer metal board, and the modified coefficient of thermal expansion of the composite multi-layer metal board is proximate to the substrate coefficient of thermal expansion.
    Type: Application
    Filed: May 26, 2023
    Publication date: May 30, 2024
    Inventors: Ai-Sen LIU, Hsiang-An FENG, Cheng-Yu CHUNG, Ya-Li CHEN
  • Publication number: 20240173034
    Abstract: Systems, apparatuses, and methods disclosed herein may be directed to clips for medical implementation, including clips for a portion of a heart. The clips may be configured to close the portion of the heart, to reduce blood flow therethrough as well as passage of clots or other undesired materials. In examples, the clips may be configured to close the left atrial appendage (LAA). The closure of the LAA may reduce the possibility of stroke or other maladies stemming from fluid flow with the LAA. In examples, the clips may be positioned exterior of the LAA, to extend over an outer surface of the LAA for closure.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Harvey H. Chen, Manouchehr A. Miraki, Rodolfo Rodriguez, Erin E. Castioni, Maria L. Saravia, Stephen Epstein, Luke Anthony Zanetti, Ashley Nicolette Hinga (formerly Keffer), Stephen Cournane, Felino V. Cortez, JR., Nancy Ling Chung, Daniel Yasevac, Andrew Ryan, Slava Arabagi, Jaime L. Baluyot, Sooji Van Echten, Da-Yu Chang, John Richard Carpenter, Sai Prasad Uppalapati, Pui Tong Ho, Jason Thai Le, Adam J. Yestrepsky
  • Publication number: 20240173795
    Abstract: A cavity forming method includes the steps of: providing the material modification processing device; according to the cavity topography of the workpiece, utilizing the material modification processing device to perform local modification including: calculating the laser-light shaping and scanning information, and based on the laser-light shaping and scanning information to have the optical axis adjustment unit to adjust positions of the laser-light shaping and scanning processing module and the processing stage, such that the area of the workpiece to be projected by the Bessel beam can be formed as the modified area; and, etching the modified area to form a cavity of the cavity topography. In additional, a material modification processing device is also provided.
    Type: Application
    Filed: December 21, 2022
    Publication date: May 30, 2024
    Inventors: FU-LUNG CHOU, Chien-Jung Huang, Yu-Chung Lin
  • Patent number: 11995246
    Abstract: A method for touchless gesture recognition is provided. The method includes transmitting ultrasonic signals via a speaker. The method includes generating ultrasonic signals. The method includes receiving the reflected ultrasonic signals from an object via two or more microphones. The method includes computing a frequency shift according to the reflected ultrasonic signals. The method includes identifying a gesture that corresponds to a movement of the object according to the frequency shift. The method includes performing a function that corresponds to the gesture.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: May 28, 2024
    Assignee: FORTEMEDIA, INC.
    Inventors: Yu-Xuan Xu, Ching-Lung Chan, Shih-Chung Wang, Yen-Son Paul Huang, Shih-Chin Gong
  • Publication number: 20240170526
    Abstract: A back side illumination (BSI) image sensor includes an epitaxial substrate, a deep trench isolation (DTI) structure from one surface to the other surface of the epitaxial substrate, a buried oxide layer on the epitaxial substrate, an epitaxial layer, a well region, a floating diffusion (FD) region, a shallow trench isolation (STI) structure, and vertical transfer gates (VTGs). The buried oxide layer has openings exposing the epitaxial substrate, and the epitaxial layer is formed on the epitaxial substrate and covers the buried oxide layer. The well region is in the epitaxial layer and the epitaxial substrate. The FD region is in the well region above the buried oxide layer, and a width of the buried oxide layer is larger than that of the FD region. The STI structure is in the epitaxial layer. The VTGs are in the epitaxial layer and through the openings of the buried oxide layer.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 23, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih-Ping Chung, Saysamone Pittikoun, Chih-Hao Peng, Ming-Yu Ho
  • Publication number: 20240170071
    Abstract: A processing device is operatively coupled to an array of memory cells. The processing device determines that a media endurance metric value for a string of the array of memory cells satisfies a first threshold criterion based on a first threshold value. The processing device further controls, based on the media endurance metric value, a ramp rate of a program pulse applied to a wordline of the string.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 23, 2024
    Inventors: Yu-Chung Lien, Joshua Garrison, Zhenming Zhou
  • Patent number: D1028971
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 28, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hsing-Yi Kao, Ming-Chung Liu, Yu-Hsin Chen