Patents by Inventor Yu-Chung C. Liao
Yu-Chung C. Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7908460Abstract: A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.Type: GrantFiled: May 3, 2010Date of Patent: March 15, 2011Assignee: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng, Timothy J. Van Hook
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Publication number: 20100217954Abstract: A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.Type: ApplicationFiled: May 3, 2010Publication date: August 26, 2010Applicant: Nintendo Co., Ltd.,Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng, Timothy J.. Van Hook
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Patent number: 7739480Abstract: A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.Type: GrantFiled: January 11, 2005Date of Patent: June 15, 2010Assignee: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng, Timothy J. Van Hook
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Patent number: 7581084Abstract: A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.Type: GrantFiled: May 21, 2004Date of Patent: August 25, 2009Assignee: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng
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Patent number: 6859862Abstract: A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.Type: GrantFiled: April 7, 2000Date of Patent: February 22, 2005Assignee: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng, Peter Hsu
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Patent number: 6857061Abstract: A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.Type: GrantFiled: April 7, 2000Date of Patent: February 15, 2005Assignee: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng
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Patent number: 6701424Abstract: A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.Type: GrantFiled: April 7, 2000Date of Patent: March 2, 2004Assignee: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng
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Patent number: 6681296Abstract: A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.Type: GrantFiled: August 1, 2001Date of Patent: January 20, 2004Assignee: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng, Peter Hsu
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Patent number: 6571328Abstract: A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.Type: GrantFiled: August 1, 2001Date of Patent: May 27, 2003Assignee: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng, Timothy J. Van Hook
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Publication number: 20020062424Abstract: A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.Type: ApplicationFiled: August 1, 2001Publication date: May 23, 2002Applicant: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng, Peter Hsu
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Publication number: 20020032848Abstract: A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.Type: ApplicationFiled: August 1, 2001Publication date: March 14, 2002Applicant: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng, Timothy J. Van Hook
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Publication number: 20020026569Abstract: A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.Type: ApplicationFiled: August 1, 2001Publication date: February 28, 2002Applicant: Nintendo Co., Ltd.Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng
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Patent number: 6112300Abstract: Multi-way branching is implemented via a single instruction by providing a computer system with a hardware token-to-address table, loading the table with branch target data correlating to the multi-way branch instruction, including software for execution with at least one multi-way branch instruction executing that branch instruction by accessing the table. The computer system is conventionally supplied with branch logic and general purpose register stack with a multi-ported output interface. The hardware resource added implementing the multi-way branch operation includes the table in the form of addressable storage comprising a plurality of multi-byte locations with a write data input and a read data output. A decoder is connected between one port of the general purpose register interface with an output to select one of the multi-byte locations for an input or output operation. The write data input of the addressable storage or table is connected to another port of the general purpose register interface.Type: GrantFiled: June 3, 1998Date of Patent: August 29, 2000Assignee: International Business Machines CorporationInventors: Thomas E. Cook, Yu-Chung C. Liao, Peter A. Sandon