Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A microfluidic detection unit comprises at least one fluid injection section, a fluid storage section and a detection section. Each fluid injection section defines a fluid outlet; the fluid storage section is in gas communication with the atmosphere and defines a fluid inlet; the detection section defines a first end in communication with the fluid outlet and a second end in communication with the fluid inlet. A height difference is defined between the fluid outlet and the fluid inlet along the direction of gravity. When a first fluid is injected from the at least one fluid injection section, the first fluid is driven by gravity to pass through the detection section and accumulate to form a droplet at the fluid inlet, such that a state of fluid pressure equilibrium of the first fluid is established.

Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate. The protective layer and the photoresist layer are selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer. The protective layer includes a polymer without a nitrogen-containing moiety, and a basic quencher, an organic acid, a photoacid generator, or a thermal acid generator.

Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value

Abstract: The methods and configurations herein provide for analysis of microplate based assays. Certain aspects include: an optical illumination panel; a plurality of sample wells configured to receive light from the optical illumination panel, and wherein the plurality of sample wells is configured with a first field of view; at least one aperture array configured to isolate directed light therethrough the plurality of sample wells; at least one optical array configured to receive optical information from the plurality of sample platforms, wherein the at least optical array comprises an array of individual microprisms configured with equal apex angles at distal equidistances along a row, wherein the individual microprism apex angles decrease toward the center of the row culminating in at least one flat surface along a center portion of the row; and a detector configured to capture the optical information with a second field of view as provided by the at least one optical array.

Abstract: A discharge apparatus is provided. A second discharge path is provided by a second discharge circuit started by a voltage across on a first discharge path provided by a first discharge circuit, so as to discharge a load capacitor.

Abstract: A conducting switch mechanism includes a housing, an operating stem is exposed from the housing, a fixed terminal set, a movable terminal module, a fulcrum bar, and an elastic member. The fixed terminal set is fixed on a base of the housing, and includes a pair of constant contact terminals, a pair of first pathway terminals, and a pair of second pathway terminals. The movable terminal module has a first movable terminal, a second movable terminal, and an insulating member. The insulating member partially clads the movable terminals. The structures of movable terminals are integrally stamped. One end of the movable terminals correspondingly abuts against the constant contact terminals, and another end of the movable terminals correspondingly contacts the first pathway terminal or the second pathway terminal. The elastic member is connected between the fulcrum bar and the movable terminal module.

Abstract: A power over Ethernet device is provided. The power over Ethernet device includes a first Ethernet connector, an Ethernet transformer circuit, and a detection circuit. The first Ethernet connector is coupled to a second Ethernet connector of a network device via an Ethernet cable and has a first reserve pin and a second reserve pin. The Ethernet transformer circuit is coupled to the first Ethernet connector to provide a supply voltage to the Ethernet cable to transfer the supply voltage to the network device. The detection circuit receives the supply voltage and is coupled to the Ethernet transformer circuit, the first reserve pin, and the second reserve pin to provide a reference voltage to the first reserve pin and receives an identification voltage from the second reserve pin to determine whether the network device is a powered device.

Abstract: A conducting switch mechanism includes a housing, an operating stem is exposed from the housing, a fixed terminal set, a movable terminal module, a fulcrum bar, and an elastic member. The fixed terminal set is fixed on a base of the housing, and includes a pair of constant contact terminals, a pair of first pathway terminals, and a pair of second pathway terminals. The movable terminal module has a first movable terminal, a second movable terminal, and an insulating member. The insulating member partially clads the movable terminals. The structures of movable terminals are integrally stamped. One end of the movable terminals correspondingly abuts against the constant contact terminals, and another end of the movable terminals correspondingly contacts the first pathway terminal or the second pathway terminal. The elastic member is connected between the fulcrum bar and the movable terminal module.

Abstract: A multiprocessor system includes a first set of processors and a second set of processors. The first set of processors include a first set of standard cells and is configured to operate in a first frequency range. The second set of processors include a second set of standard cells and is configured to operate in a second frequency range. The first set of processors and the second set of processors have the same register-transfer level (RTL) description. Cells in the first set of standard cells have corresponding cells in the second set of standard cells with different characteristics. The first frequency range includes one or more frequencies higher than a maximum frequency in the second frequency range. The system also includes a clock generator that provides the same frequency to the first set of processors and the second set of processors.

Abstract: A power over Ethernet device is provided. The power over Ethernet device includes a first Ethernet connector, an Ethernet transformer circuit, and a detection circuit. The first Ethernet connector is coupled to a second Ethernet connector of a network device via an Ethernet cable and has a first reserve pin and a second reserve pin. The Ethernet transformer circuit is coupled to the first Ethernet connector to provide a supply voltage to the Ethernet cable to transfer the supply voltage to the network device. The detection circuit receives the supply voltage and is coupled to the Ethernet transformer circuit, the first reserve pin, and the second reserve pin to provide a reference voltage to the first reserve pin and receives an identification voltage from the second reserve pin to determine whether the network device is a powered device.

Abstract: A discharge apparatus is provided. A second discharge path is provided by a second discharge circuit started by a voltage across on a first discharge path provided by a first discharge circuit, so as to discharge a load capacitor.

Abstract: The methods and configurations herein provide for analysis of microplate based assays. Certain aspects include: an optical illumination panel; a plurality of sample wells configured to receive light from the optical illumination panel, and wherein the plurality of sample wells is configured with a first field of view; at least one aperture array configured to isolate directed light therethrough the plurality of sample wells; at least one optical array configured to receive optical information from the plurality of sample platforms, wherein the at least optical array comprises an array of individual microprisms configured with equal apex angles at distal equidistances along a row, wherein the individual microprism apex angles decrease toward the center of the row culminating in at least one flat surface along a center portion of the row; and a detector configured to capture the optical information with a second field of view as provided by the at least one optical array.

Abstract: A method for performing system power control within an electronic device and an associated apparatus are provided. The method includes the steps of: utilizing a power consumption index generator positioned in a specific subsystem to generate a power consumption index corresponding to the specific subsystem, where the electronic device includes a plurality of subsystems, and the specific subsystem is one of the plurality of subsystems; and triggering a power limiter protection operation for the electronic device according to the power consumption index. For example, the power consumption index corresponding to the specific subsystem may represent a power consumption value of the specific subsystem, and the method may further include: comparing the power consumption value of the specific subsystem with a peak power threshold to determine whether the power consumed by the specific subsystem reaches the peak power threshold to generate a determining result, for triggering the power limiter protection operation.

Abstract: A method for performing system power control within an electronic device and an associated apparatus are provided. The method includes the steps of: utilizing a power consumption index generator positioned in a specific subsystem to generate a power consumption index corresponding to the specific subsystem, where the electronic device includes a plurality of subsystems, and the specific subsystem is one of the plurality of subsystems; and triggering a power limiter protection operation for the electronic device according to the power consumption index. For example, the power consumption index corresponding to the specific subsystem may represent a power consumption value of the specific subsystem, and the method may further include: comparing the power consumption value of the specific subsystem with a peak power threshold to determine whether the power consumed by the specific subsystem reaches the peak power threshold to generate a determining result, for triggering the power limiter protection operation.

Abstract: A method for performing system power budgeting within an electronic device and an associated apparatus are provided. The method includes the steps of: utilizing a power consumption index generator positioned in a specific subsystem to generate a power consumption index corresponding to the specific subsystem, where the electronic device includes a plurality of subsystems, and the specific subsystem is one of the plurality of subsystems; and performing configuration adjustment on at least one portion of the electronic device according to the power consumption index corresponding to the specific subsystem.

Abstract: A method for performing system power budgeting within an electronic device and an associated apparatus are provided. The method includes the steps of: utilizing a power consumption index generator positioned in a specific subsystem to generate a power consumption index corresponding to the specific subsystem, where the electronic device includes a plurality of subsystems, and the specific subsystem is one of the plurality of subsystems; and performing configuration adjustment on at least one portion of the electronic device according to the power consumption index corresponding to the specific subsystem.

Abstract: A multiprocessor system includes a first set of processors and a second set of processors. The first set of processors include a first set of standard cells and is configured to operate in a first frequency range. The second set of processors include a second set of standard cells and is configured to operate in a second frequency range. The first set of processors and the second set of processors have the same register-transfer level (RTL) description. Cells in the first set of standard cells have corresponding cells in the second set of standard cells with different characteristics. The first frequency range includes one or more frequencies higher than a maximum frequency in the second frequency range. The system also includes a clock generator that provides the same frequency to the first set of processors and the second set of processors.

Abstract: A syringe includes a sleeve and a pressure vessel with high pressure fluid therein. The sleeve further comprises a sleeve piston. As the high pressure vessel contacts the sleeve piston, and a bump on the sleeve piston destroys the airtight status of the high pressure vessel. While the seal of the high pressure vessel is removed, the compressed fluid flows into the sleeve through the opening of the high pressure vessel and the hole of the sleeve piston. When the closed end of the sleeve moves closer to the closed end of the sleeve piston, the fluid in the sleeve is pressed and flows out of the sleeve through the sleeve hole of the sleeve.

Abstract: An integrated LED lamp and a data transmission circuit and a synchronization circuit thereof are provided. Integrated LEDs of the present invention only need two pins, such that the originally existing LED package method can be adopted. In addition, by using two pins, the present invention can synchronize the LEDs or further update a displayed pattern. Because the old package technology has been well developed, the present invention can avoid the risk of the yield reduction caused by the new package technology in addition to reductions of the wire and the manufacturing cost.