Abstract: One aspect of the present disclosure pertains to an integrated (IC) structure. The IC structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (RDL) structure formed over the interconnect structure. The RDL structure includes: a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a RDL top portion over the RDL pad portion and the RDL signal routing portion. The multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.

Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.