Abstract: A light emission apparatus includes a laser diode configured to emit a light; a laser driver electrically coupled to the laser diode, the laser driver being configured to drive the laser diode to generate the light; and an optical module arranged to receive the light emitted by the laser diode, the optical module comprising at least one optical element and being configured to adjust the light and emits a transmitting light; wherein the transmitting light emits from the optical module with an illumination angle and the optical module adjusts the light to vary the illumination angle.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: A method and system for robot motion control using a model predictive control (MPC) technique including torque rate control and suppression of end tooling oscillation. An MPC module includes a robot dynamics model which inherently reflects response nonlinearities associated with changes in robot configuration, and an optimization solver having an objective function with a torque rate term and inequality constraints defining bounds on both torque and torque rate. The torque rate control in the MPC module provides an effective means of controlling jerk in robot joints, while accurately modeling robot dynamics as the robot changes configuration during a motion program. End tooling oscillation dynamics may also be included in the MPC objective function and constraints in order to automatically control end tooling vibration in the calculations of the MPC module.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A dual mode charge control method includes steps of: detecting an input voltage of the resonance tank, a resonance current of the resonance tank, an output current of the load, and an output voltage of the load; performing a single-band charge control when determining a light-load condition or a no-load condition of the load according to the output current; compensating the output voltage to generate an upper threshold voltage in the single-band charge control, and acquiring a resonance voltage by calculating the resonance current by a resettable integrator; comparing the resonance voltage and the upper threshold voltage to generate a first control signal; generating a second control signal complementary to the first control signal by a pulse-width modulation duplicator; providing the first control signal and the second control signal to respectively control a first power switch and a second power switch of the resonance circuit.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A development system and a method of an offline software-in-the-loop simulation are disclosed. A common firmware architecture generates a chip control program. The common firmware architecture has an application layer and a hardware abstraction layer. The application layer has a configuration header file and a product program. A processing program required by a peripheral module is added to the hardware abstraction layer during compiling. The chip control program is provided to a controller chip or a circuit simulation software to be executed to control the product-related circuit through controlling the peripheral module.

Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: A fluid-cooled battery system includes at least one battery module which includes a plurality of rows of battery cells, an outer casing, and at least one cell fixture. The outer casing defines therein an accommodation space. The cell fixture includes a holding web fitted inside the accommodation space, and formed with a plurality of rows of retaining holes. The retaining holes of each row are configured to retain cell bodies of a respective row of the battery cells so as to permit the battery cells to be held in the accommodation space by the holding web, to thereby keep the battery cells in stable position against undesired vibration.

Abstract: A fluid-cooled battery system includes at least one battery module which includes a plurality of rows of battery cells, an outer casing, and at least one cell fixture. The outer casing defines therein an accommodation space. The cell fixture includes a holding web fitted inside the accommodation space, and formed with a plurality of rows of retaining holes. The retaining holes of each row are configured to retain cell bodies of a respective row of the battery cells so as to permit the battery cells to be held in the accommodation space by the holding web, to thereby keep the battery cells in stable position against undesired vibration.

Abstract: A method for generating Bessel beams includes the steps of: utilizing a light source to generate an incident beam to a phase modulation module; utilizing the phase modulation module to rectify the incident beam into a circular beam, and to modulate a phase of the circular beam into an asymmetric phase so as to form an asymmetric collimated circular beam provided to a scanning module; utilizing the scanning module to compensate the asymmetric collimated circular beam, and utilizing the asymmetric collimated circular beam to scan at different angles and then enter a focusing element; and, utilizing the focusing element to focus and interfere the asymmetric collimated circular beam into form a Bessel beam for machining.

Abstract: A Raman spectroscopy system, including an optical excitation source, an objective lens, a mirror for redirecting optical excitation to the objective lens, an optical switch, an excitation beam optical fiber operationally connected to the objective lens and to the optical switch, a plurality of Raman probes, a plurality of probe optical fibers, each respective probe optical fiber operationally connected to the optical switch and a respective Raman probe, and a spectrometer. Each respective Raman probe is operationally connected to the spectrometer.

Abstract: A method of determining the contributions of multiple incident photons to an output of a sensor, including providing a photonic sensor having a sensor input and capable of generating an electrical signal proportional to a number of photons interacting with the photonic sensor input as a function of time, calibrating the photonic sensor such that a response of the photonic sensor to a single photon detected is in a waveform having an amplitude and a time, wherein the product of the amplitude and the time is statistically bounded, determining a probabilistic boundary between one or more of electrical, optical, and thermal sources of noise of the sensor, acquiring a response wave form from the photonic sensor through analog-to-digital conversion with a resolution in amplitude and time corresponding to accuracy required in quantifying the response wave form, storing each acquired response wave form, individually, in a format selected from the group consisting of real-time and buffered packets in digital form, and

Abstract: A method of fabricating a substrate having a through via includes: providing a carrier board having a release layer thereon; attaching the substrate onto the carrier board via the release layer; applying a light beam to the substrate to form a first blind hole in the substrate, wherein the first blind hole penetrates a first surface and a second surface of the substrate; performing an enlargement process on the first blind hole to form a second blind hole; forming a through via in the second blind hole; and performing a de-bonding process to release the substrate having a through via from the carrier board.

Abstract: A controller of a touch display device is configured to perform steps of: transmitting a main uplink signal to an input device, the main uplink signal indicating an amount of a plurality of downlink signals transmitted in a frame; transmitting a first sub-uplink signal to the input device, the first sub-uplink signal notifying the input device of a time length of a first downlink signal among the plurality of downlink signals; transmitting a second sub-uplink signal to the input device, the second sub-uplink signal notifying the input device of a time length of a second downlink signal among the plurality of downlink signals; and receiving the plurality of downlink signals from the input device.

Abstract: A cutting method for forming a chamfered corner includes a step of selecting a light pattern-adjusting module according to a pre-cut chamfer angle, a step of the light pattern-adjusting module emitting a laser beam to a substrate and thus forming a modified region extending in a thickness direction at the substrate, a step of the light pattern-adjusting module adjusting an axial energy distribution of a light pattern of the laser beam to vary an appearance of the modified region so as to form the modified region fulfilling the pre-cut chamfer angle, and a step of etching the substrate having the modified region to form a chamfered surface on the substrate by cutting the modified region from the substrate.