Abstract: A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.

Abstract: An integrated circuit (IC) device includes memory cells each including first through fourth memory elements. The first memory element is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line. The second memory element is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor. The first and second memory elements are arranged in a first row along the first axis. The third memory element is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor electrically coupled to the first conductor. The fourth memory element is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line. The third and fourth memory elements are arranged, along the first axis, in a second row spaced from the first row along an axis transverse to the first axis.

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.

Abstract: A device capable of correcting wrong normal vectors of an original three-dimensional scan result includes a normal vector generation unit and a correction unit, wherein the original three-dimensional scan result corresponds to an object. The normal vector generation unit is used for generating a normal vector corresponding to each point of the original three-dimensional scan result according to the each point of the original three-dimensional scan result and a plurality of predetermined points of the original three-dimensional scan result adjacent to the each point of the original three-dimensional scan result. The correction unit is coupled to the normal vector generation unit for determining an inner region of the original three-dimensional scan result, and reversing a normal vector corresponding to a point of the original three-dimensional scan result when the normal vector corresponding to the point is toward the inner region of the original three-dimensional scan result.

Abstract: A device capable of correcting wrong normal vectors of an original three-dimensional scan result includes a normal vector generation unit and a correction unit, wherein the original three-dimensional scan result corresponds to an object. The normal vector generation unit is used for generating a normal vector corresponding to each point of the original three-dimensional scan result according to the each point of the original three-dimensional scan result and a plurality of predetermined points of the original three-dimensional scan result adjacent to the each point of the original three-dimensional scan result. The correction unit is coupled to the normal vector generation unit for determining an inner region of the original three-dimensional scan result, and reversing a normal vector corresponding to a point of the original three-dimensional scan result when the normal vector corresponding to the point is toward the inner region of the original three-dimensional scan result.