Patents by Inventor Yu-Fang Hsia

Yu-Fang Hsia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9826632
    Abstract: A multi-layer substrate structure to achieve multiple arrangements of power/ground domains is disclosed. The multi-layer substrate structure comprises a first layer for disposing an integrated circuit thereon and a second layer coupled to the first layer, wherein a connection structure is electrically connected to a plurality of power/ground domains on the second layer. With different combinations of the sawing lines and keep-out regions on the multi-layer substrate structure for cutting off some portions of the connection structure, the invention can achieve multiple arrangements of power/ground domains without impacting the customer's PCB or system board design so as to cut short the cycle time for engineering development phase.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 21, 2017
    Assignees: Global Unichip Corp., Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yu-Ru Chang, Yu-Fang Hsia, Ling-Chih Chou
  • Publication number: 20160219699
    Abstract: A multi-layer substrate structure to achieve multiple arrangements of power/ground domains is disclosed. The multi-layer substrate structure comprises a first layer for disposing an integrated circuit thereon and a second layer coupled to the first layer, wherein a connection structure is electrically connected to a plurality of power/ground domains on the second layer. With different combinations of the sawing lines and keep-out regions on the multi-layer substrate structure for cutting off some portions of the connection structure, the invention can achieve multiple arrangements of power/ground domains without impacting the customer's PCB or system board design so as to cut short the cycle time for engineering development phase.
    Type: Application
    Filed: April 6, 2016
    Publication date: July 28, 2016
    Applicants: GLOBAL UNICHIP CORP., Taiwan Semiconductor Manufacturing Company LTD.
    Inventors: Yu-Ru Chang, Yu-Fang Hsia, Ling-Chih Chou
  • Patent number: 9345132
    Abstract: The present invention discloses a package substrate layout design to achieve multiple substrate functions for engineering development and verification. The substrate layout contains a connection structure to connect to a plurality of power/ground domains on the package substrate. With different combination of the cutting lines on the package substrate, the invention can achieve multiple substrate functions without impacting the customer's PCB or system board design and provide cost effective and fast cycle time for engineering development phase.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 17, 2016
    Assignees: Global Unichip Corp., Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yu-Ru Chang, Yu-Fang Hsia, Ling-Chih Chou
  • Publication number: 20140216802
    Abstract: The present invention discloses a package substrate layout design to achieve multiple substrate functions for engineering development and verification. The substrate layout contains a connection structure to connect to a plurality of power/ground domains on the package substrate. With different combination of the cutting lines on the package substrate, the invention can achieve multiple substrate functions without impacting the customer's PCB or system board design and provide cost effective and fast cycle time for engineering development phase.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 7, 2014
    Inventors: Yu-Ru Chang, Yu-Fang Hsia, Ling-Chih Chou