Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: A display device includes first and second display modules and first and second turning pieces that include a first coupling piece, a first turning piece, a second turning piece, and a third turning piece, a second coupling piece and a guiding device. When the first and second display modules are switched between folding and unfolding, the first turning piece pivots relative to the first coupling piece and the second turning piece, and the third turning piece pivots relative to the second coupling piece and the second turning piece. When the display module is switched from folded to unfolded, the other side of the first display module relative to the side is pulled, the side of the first display module is guided by one end of the guiding device and slides to the other end, the first and second display modules are symmetrically unfolded with the side edge as the center.

Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.

Abstract: An information handling system includes a host processing system and a Liquid Crystal Display device. The host processing system includes a graphics processing unit (GPU) and the LCD device includes a memory device and a DisplayPort Configuration Data (DPCD) register. The host processing system 1) determines whether the first GPU supports a Dynamic Display Shifting (DDS) mode, 2) when the GPU does not support the DDS mode, provides a first indication to the LCD device that the GPU does not support the DDS mode, and 3) when the GPU supports the DDS mode, provides a second indication to the LCD device that the GPU supports the DDS mode. The LCD device retrieves a Panel Self Refresh (PSR) setting from the memory device and stores the PSR setting to the DPCD register in response to the first indication, and retrieves a DDS setting from the memory and stores the DDS setting to the DPCD register in response to the second indication.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A method of making a showerhead for a semiconductor processing apparatus is disclosed. In one embodiment, the method includes providing a substrate; forming first holes in the substrate; forming a protective film on the substrate, where the protective film covers sidewalls of the first holes; and forming second holes in the substrate, where a part of the protective film within the first holes is removed. In another embodiment, the method includes providing a substrate; forming islands on the substrate; forming a protective film on the substrate, where the protective film does not cover the tops of the islands; and forming holes in the islands.

Abstract: A method of making a showerhead for a semiconductor processing apparatus is disclosed. In one embodiment, the method includes providing a substrate; forming first holes in the substrate; forming a protective film on the substrate, where the protective film covers sidewalls of the first holes; and forming second holes in the substrate, where a part of the protective film within the first holes is removed. In another embodiment, the method includes providing a substrate; forming islands on the substrate; forming a protective film on the substrate, where the protective film does not cover the tops of the islands; and forming holes in the islands.

Abstract: A worktable used in a table saw is disclosed to include a main worktable plate made of iron and having a first opening, and a relatively smaller reinforcing plate made of iron and bonded to the bottom side of the main worktable plate to hold the cutting mechanism of the table saw at the bottom side and having a second opening in vertical alignment with the first opening for the passing of the saw blade of the cutting mechanism.

Abstract: A sinter furnace for sapphire crystal growth includes an outer furnace, and an inner furnace mounted in the outer furnace. The inner furnace includes a furnace bed, a furnace body detachably mounted on the furnace bed, a gas inlet pipe mounted in the furnace body, and a gas outlet pipe mounted on the furnace body. Thus, the inert gas is introduced through the gas inlet pipe into the furnace body and the used inert gas is drained outwardly from the gas outlet pipe to enhance the air circulation in the furnace body so that the heat contained in the furnace body is distributed evenly so as to enhance the quality of the sapphire crystal.

Abstract: A sapphire crystal growth method includes a first step of grinding, a second step of purification, a third step of spraying and drying particles, a fourth step of adding organic bonding agent, a fifth step of press molding, and a sixth step of crystal growth. Thus, the sapphire crystal growth method has a shorter crystal growth time than that of the conventional crystal growth method. In addition, the sapphire crystal growth method has a lower price, has crystals whose mass and size are unlimited, and has a higher quality.

Abstract: A sensor strip with capillary flow control has a base layer having a plurality of conductive paths delineated thereon, an electrode forming layer disposed on the base layer, the electrode forming layer having a first opening forming a working electrode, a second opening forming a reference electrode, and a flow-control mechanism, a spacer layer disposed on the electrode forming layer, and a cover layer with a vent opening disposed on the spacer layer and forming a substantially flat sample channel with walls formed by the electrode forming layer, the spacer layer and the cover layer, the substantially flat sample chamber having a sample inlet adjacent a proximal end and the vent opening adjacent a distal end where the substantially flat sample chamber contains the working electrode, the reference electrode and the flow-control mechanism.