Abstract: A light module includes a light guide plate, a first light source and a second light source. The light guide plate has an inner light emitting surface, an outer light emitting surface opposite to the inner light emitting surface, and a light incident surface connecting the inner light emitting surface and the outer light emitting surface. The first light source is disposed on the light incident surface and located between the inner light emitting surface and the outer light emitting surface, and the first light source emits light of a first color temperature. The second light source is disposed on the light incident surface and located between the first light source and the inner light emitting surface, and the second light source emits light of a second color temperature, and the difference between the first color temperature and the second color temperature is greater than 2000K.

Abstract: A display device includes a reflective display panel, a light guide plate, a light source, and a first optical adhesive layer. The light guide plate is located on the reflective display device. The light guide plate has a top surface, a bottom surface and a light incident surface connecting the top surface and the bottom surface. The light guide plate further includes multiple microstructures located on the top surface and multiple lenticular structures located on the bottom surface. The light source faces the light incident surface of the light guide plate. The first optical adhesive layer is located below the light guide plate and in contact with the lenticular structure. A refractive index of the first optical adhesive layer is lower than a refractive index of the light guide plate.

Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.

Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.