Patents by Inventor Yu-Feng Lin
Yu-Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240249948Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.Type: ApplicationFiled: March 28, 2024Publication date: July 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Wei CHANG, Kao-Feng LIN, Min-Hsiu HUNG, Yi-Hsiang CHAO, Huang-Yi HUANG, Yu-Ting LIN
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Patent number: 12040006Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.Type: GrantFiled: July 26, 2022Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chao-I Wu, Sheng-Chen Wang, Yu-Ming Lin
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Patent number: 12041783Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.Type: GrantFiled: August 4, 2022Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Lu, Han-Jong Chia, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin
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Publication number: 20240222253Abstract: A semiconductor power component includes a ceramic-metal composite substrate, a vertical transistor and a filler. The ceramic-metal composite substrate includes a ceramic insulating layer, a heat-dissipating metal layer, a bonding metal layer and a metal element. The metal element is connected to the bonding metal layer, and the bonding metal layer is located between the ceramic insulating layer and the metal element. The vertical transistor is connected to the bonding metal layer. The vertical transistor includes a conductive pad. The conductive pad is electrically connected to the bonding metal layer. The at least one metal element and the bonding metal layer are integrally formed into one.Type: ApplicationFiled: December 12, 2023Publication date: July 4, 2024Inventors: Yu-Feng LIN, Cheng-Chuan CHEN
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Patent number: 11966352Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.Type: GrantFiled: October 8, 2020Date of Patent: April 23, 2024Assignee: Dell Products L.P.Inventors: Yu-Feng Lin, Hao-Cheng Ku, Yi-Wei Lu
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Publication number: 20240069387Abstract: A display device includes a touch panel, an optical adhesive layer, and a front light module that includes a light source and a light guide plate (LGP) including multiple microstructures recessed into the LGP from a first surface of the LGP to form voids. The optical adhesive layer is adhered between the touch panel and a first surface of the LGP. A surface of the optical adhesive layer facing the LGP is in contact with the first surface of the LGP in multiple first regions, and a surface of the optical adhesive layer facing the LGP and the plurality of microstructures being overlapped in multiple second regions. A maximum vertical distance between each void and the first surface is a first depth. A vertical distance between the first regions and the second regions is 0 to 0.7 times the first depth.Type: ApplicationFiled: July 12, 2023Publication date: February 29, 2024Applicant: Coretronic CorporationInventors: Tzeng-Ke Shiau, Yu-Feng Lin, Ying-Shun Syu, Che-Jui Hsu
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Publication number: 20240047302Abstract: A power chip package and a power module are provided. The power chip package includes a metal cover, a power chip, and a thermal conductive material. A recess is formed on a side surface of the metal cover. The power chip is bonded on the metal cover and is located in the recess. The thermal conductive material fills the recess and surrounds the power chip. At least one first electrode of the power chip is exposed out of the thermal conductive material. The power module includes a circuit board, plural power chip packages and a polymeric resin. The power chip packages are disposed on the circuit board. The polymeric resin packages the power chip packages on the circuit board.Type: ApplicationFiled: July 29, 2023Publication date: February 8, 2024Inventors: Cheng-Chuan CHEN, Yu-Feng LIN
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Publication number: 20230413474Abstract: Information handling system thermal management of processing components, such as CPU, GPU and/or memory, by a liquid cooling system is protected by a leak detection enclosure having a leak detection sensor disposed in an interior. The leak detection enclosure has a frame coupled to a cold plate that encloses the leak detection sensor and cooling fluid hose fittings so that leaked fluid is trapped within the enclosure for detection by the leak detection sensor. A planar cover couples to the frame upper side over the leak detection circuit and the cooling fluid hose fittings to provide ready assembly and an inexpensive adaptable form factor.Type: ApplicationFiled: May 25, 2022Publication date: December 21, 2023Applicant: Dell Products L.P.Inventors: Peter Clark, Kuang-Hsi Lin, Yu-Feng Lin, Rui-Shen Lu, lou-Ren Su, Hung-Wen Wu
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Publication number: 20230006109Abstract: A light emitting device and a manufacturing method thereof are provided. The light emitting device includes a light emitting unit, a fluorescent layer, a reflective layer, and a light-absorbing layer. The light emitting unit has a top surface, a bottom surface opposite to the top surface, and a side surface located between the top surface and the bottom surface. The light emitting unit includes an electrode disposed at the bottom surface. The fluorescent layer is disposed on the top surface of the light emitting unit. The reflective layer covers the side surface of the light emitting unit. The light-absorbing layer covers the reflective layer, so that the reflective layer is located between the side surface of the light emitting unit and the light-absorbing layer.Type: ApplicationFiled: June 24, 2022Publication date: January 5, 2023Applicant: Genesis Photonics Inc.Inventors: Yun-Han Wang, Chin-Hua Hung, Chuan-Yu Liu, Tsai-Chieh Shih, Jui-Fu Chang, Yu-Jung Wu, Yu-Feng Lin
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Publication number: 20220114130Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.Type: ApplicationFiled: October 8, 2020Publication date: April 14, 2022Applicant: Dell Products L.P.Inventors: Yu-Feng Lin, Hao-Cheng Ku, Yi-Wei Lu
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Electronic device control method and electronic device applying the electronic device control method
Patent number: 11282475Abstract: An electronic device control method applied to an electronic device can operate in a display mode and a touch sensing mode. The method comprises: (a) controlling the electronic device to have a first mode switch frequency; and (b) controlling the electronic device to have a second mode switch frequency different from the first mode switch frequency. The first mode switch frequency and the second mode switch frequency are frequencies for switching between the display mode and the touch sensing mode.Type: GrantFiled: July 23, 2019Date of Patent: March 22, 2022Assignee: HIMAX TECHNOLOGIES LIMITEDInventors: Chih-Ming Wu, Yaw-Guang Chang, Chin-Jung Chen, Yu-Feng Lin, Chung-Wen Chang -
Publication number: 20210159369Abstract: A light emitting device includes a wavelength conversion layer, at least one light emitting unit and a reflective protecting element. The wavelength conversion layer has an upper surface and a lower surface opposite to each other. The light emitting unit has two electrode pads located on the same side of the light emitting unit. The light emitting unit is disposed on the upper surface of the wavelength conversion layer and exposes the two electrode pads. The reflective protecting element encapsulates at least a portion of the light emitting unit and a portion of the wavelength conversion layer, and exposes the two electrode pads of the light emitting unit.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Applicant: Genesis Photonics Inc.Inventors: Cheng-Wei Hung, Chin-Hua Hung, Long-Chi Du, Jui-Fu Chang, Po-Tsun Kuo, Hao-Chung Lee, Yu-Feng Lin
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Patent number: 10957674Abstract: A manufacturing method is provided. The manufacturing method includes the following steps. Firstly, a substrate and a light-emitting component are provided, wherein the light-emitting component is disposed on the substrate. Then, a wavelength conversion layer is provided, wherein the wavelength conversion layer includes a high-density phosphor layer and a low-density phosphor layer. Then, the high-density phosphor layer is adhered to the light-emitting component by an adhesive. Then, a reflective layer is formed above the substrate, wherein the reflective layer covers a lateral surface of the light-emitting component, a lateral surface of the adhesive and a lateral surface of the wavelength conversion layer.Type: GrantFiled: December 2, 2019Date of Patent: March 23, 2021Assignee: GENESIS PHOTONICS INCInventors: Cheng-Wei Hung, Jui-Fu Chang, Chin-Hua Hung, Yu-Feng Lin
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Patent number: 10910523Abstract: A light emitting device includes a wavelength conversion layer, at least one light emitting unit and a reflective protecting element. The wavelength conversion layer has an upper surface and a lower surface opposite to each other. The light emitting unit has two electrode pads located on the same side of the light emitting unit. The light emitting unit is disposed on the upper surface of the wavelength conversion layer and exposes the two electrode pads. The reflective protecting element encapsulates at least a portion of the light emitting unit and a portion of the wavelength conversion layer, and exposes the two electrode pads of the light emitting unit.Type: GrantFiled: June 11, 2018Date of Patent: February 2, 2021Assignee: Genesis Photonics Inc.Inventors: Cheng-Wei Hung, Chin-Hua Hung, Long-Chi Du, Jui-Fu Chang, Po-Tsun Kuo, Hao-Chung Lee, Yu-Feng Lin
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ELECTRONIC DEVICE CONTROL METHOD AND ELECTRONIC DEVICE APPLYING THE ELECTRONIC DEVICE CONTROL METHOD
Publication number: 20210027740Abstract: An electronic device control method applied to an electronic device can operate in a display mode and a touch sensing mode. The method comprises: (a) controlling the electronic device to have a first mode switch frequency; and (b) controlling the electronic device to have a second mode switch frequency different from the first mode switch frequency. The first mode switch frequency and the second mode switch frequency are frequencies for switching between the display mode and the touch sensing mode.Type: ApplicationFiled: July 23, 2019Publication date: January 28, 2021Inventors: Chih-Ming Wu, Yaw-Guang Chang, Chin-Jung Chen, Yu-Feng Lin, Chung-Wen Chang -
Patent number: 10854780Abstract: A light emitting device including a light emitting unit and a phosphor resin layer is provided. The light emitting unit has a top surface and a bottom surface opposite to each other. Each of the light emitting units includes two electrodes. The two electrodes are disposed on the bottom surface. The phosphor resin layer is disposed on the top surface of the light emitting unit. One side of the phosphor resin layer has a mark. One of the two electrodes is closer to the mark with respect to the other one of the two electrodes.Type: GrantFiled: November 5, 2018Date of Patent: December 1, 2020Assignee: Genesis Photonics Inc.Inventors: Cheng-Wei Hung, Chin-Hua Hung, Xun-Xain Zhan, Chuan-Yu Liu, Yun-Chu Chen, Yu-Feng Lin
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Patent number: 10784423Abstract: A light emitting device including a first light emitting unit, a second light emitting unit, a heat dissipation substrate, a plurality of first bumps and a plurality of second bumps is provided. The heat dissipation substrate is disposed between the first light emitting unit and the second light emitting unit. The first bumps are connected between the first light emitting unit and the heat dissipation substrate. The second bumps are connected between the second light emitting unit and the heat dissipation substrate.Type: GrantFiled: November 5, 2018Date of Patent: September 22, 2020Assignee: GENESIS PHOTONICS INC.Inventors: Cheng-Wei Hung, Chin-Hua Hung, Xun-Xain Zhan, Chuan-Yu Liu, Yu-Feng Lin
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Publication number: 20200289425Abstract: Disclosed herein are drug-containing vesicles, each of which includes a carbon dot liposome (C-dot liposome) formed by a plurality of Janus particles, which are self-assembled into the C-dot liposome; and a drug encapsulated within the C-dot liposome. Also disclosed herein is a method of producing the drug-containing vesicles. The method includes, mixing a plurality of Janus particles with a drug solution (e.g., an anti-cancer drug solution) to form a mixed solution; and producing the drug-containing vesicles either by a film-hydration method or an injection method. In the film-hydration method, the mixed solution is condensed until a film-like structure is formed; and sonicating the film-like structure in a salt solution to produce the drug-containing vesicle. In the injection method, the mixed solution is rapidly injected into a salt solution to produce the drug-containing vesicle. Also encompasses in the present disclosure are methods for treating a subject afflicted with a cancer.Type: ApplicationFiled: June 3, 2020Publication date: September 17, 2020Applicant: National Taiwan UniversityInventors: Huan-Tsung CHANG, Yu-Feng LIN, Shih-Chun WEI, Yu-Ting TSENG, Yu-Feng HUANG, Chih-Ching HUANG, Yu-Syuan LIN, Tzu-Heng CHEN
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Patent number: 10723395Abstract: A split chassis system includes a first chassis base portion that is configured to house a first component and a second chassis base portion that is configured to house a second component. The second chassis base portion is positioned adjacent the first chassis base portion such that a first chassis coupling member included on the first chassis base portion is coupled to a second chassis coupling member included on the second chassis base portion. The split chassis system further includes a leveling subsystem that is coupled to the first chassis base portion and the second chassis base portion. The leveling subsystem aligns the first chassis base portion and the second chassis base portion such that the first chassis base portion and the second chassis base portion substantially maintain coplanarity when the first chassis coupling member is coupled to the second chassis coupling member.Type: GrantFiled: June 11, 2019Date of Patent: July 28, 2020Assignee: Dell Products L.P.Inventors: Corey Dean Hartman, Yu-Feng Lin
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Patent number: D886751Type: GrantFiled: March 29, 2017Date of Patent: June 9, 2020Assignee: Genesis Photonics Inc.Inventors: Hao-Chung Lee, Xun-Xain Zhan, Yu-Feng Lin