Patents by Inventor Yu-Feng Lin

Yu-Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240196625
    Abstract: A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.
    Type: Application
    Filed: February 24, 2024
    Publication date: June 13, 2024
    Inventors: Bo-Feng YOUNG, Mauricio MANFRINI, Sai-Hooi YEONG, Han-Jong CHIA, Yu-Ming LIN
  • Publication number: 20240196074
    Abstract: This disclosure provides a lens assembly that has an optical path and includes a lens element and a light-blocking membrane layer. The lens element has an optical portion, and the optical path passes through the optical portion. The light-blocking membrane layer is coated on the lens element and adjacent to the optical portion. The light-blocking membrane layer has a distal side and a proximal side that is located closer to the optical portion than the distal side. The proximal side includes two extension structures and a recessed structure. Each of the extension structures extends along a direction away from the distal side, and the extension structures are not overlapped with each other in a direction in parallel with the optical path. The recessed structure is connected to the extension structures and recessed along a direction towards the distal side.
    Type: Application
    Filed: January 26, 2024
    Publication date: June 13, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Jyun-Jia CHENG, Yu Chen LAI, Ming-Ta CHOU, Cheng-Feng LIN, Chen-Yi HUANG
  • Patent number: 12007619
    Abstract: An imaging lens system has an optical axis and an image surface through which the optical axis passes. The imaging lens system includes a plastic lens barrel surrounding the optical axis. The plastic lens barrel includes an image-side portion and an object-side aperture through which the optical axis passes, and the image-side portion is located between the image surface and the object-side aperture. The image-side portion includes a protrusive structure surrounding the optical axis and extending towards the image surface. The protrusive structure has an inner surface facing the optical axis, an outer surface disposed opposite to the inner surface and located farther away from the optical axis than the inner surface and a reflection-reducing surface extending towards the image surface and connected to and located between the inner surface and the outer surface. The protrusive structure includes a reflection-reducing structure disposed on the reflection-reducing surface.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: June 11, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Yu Chen Lai, Ming-Ta Chou, Cheng-Feng Lin
  • Publication number: 20240182079
    Abstract: An autonomous vehicle path prediction method includes sensing vehicles driving on a road and generating sensing signals corresponding to the vehicles; surrounding vehicles and a current state of the emergency vehicle and performing an emergency path prediction corresponding to the emergency vehicle when the vehicles further include the emergency vehicle; generating an emergency autonomous driving decision according to the emergency path prediction and providing an autonomous vehicle path planning corresponding to the emergency autonomous driving decision; and controlling the autonomous vehicle to change the driving path and the driving mode on the road according to the autonomous vehicle path planning.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 6, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Feng Li, Yu-Heng Lin, Yu-Hsuan Ying
  • Patent number: 12002710
    Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsin Chan, Jiing-Feng Yang, Kuan-Wei Huang, Meng-Shu Lin, Yu-Yu Chen, Chia-Wei Wu, Chang-Wen Chen, Wei-Hao Lin, Ching-Yu Chang
  • Patent number: 11994736
    Abstract: An imaging lens assembly has an optical axis and includes an annular structure located on an object side of the imaging lens assembly and surrounds the optical axis. The annular structure is located on an object side of the imaging lens assembly, surrounds the optical axis, and includes a first through hole, a second through hole, a first frustum surface, a second frustum surface and a third frustum surface. The first through hole is disposed on an object side of the annular structure, and the second through hole is disposed on an image side of the first through hole. The first frustum surface is disposed on the image side of the first through hole. The second frustum surface is disposed on an object side of the second through hole. The third frustum surface is disposed on an image side of the second through hole.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: May 28, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Yu-Chen Lai, Ming-Ta Chou, Cheng-Feng Lin, Ming-Shun Chang
  • Patent number: 11997855
    Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sheng-Chen Wang, Sai-Hooi Yeong, Yu-Ming Lin, Mauricio Manfrini, Han-Jong Chia
  • Publication number: 20240170323
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith KHADERBAD, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11986569
    Abstract: An instrument sterilization monitoring system and an instrument sterilization monitoring method are provided. The instrument sterilization monitoring system includes a server, a sterilization device, and a mobile device. An image capturing module of the mobile device is used to capture image information of a first sterilization device indication device in the sterilization device, image information of a first sterilization device indication label, image information of a second instrument indication device, and image information of a second instrument indication label which are disposed outside an instrument package. The image information is uploaded to the server. The server determines, according to the image information, whether or not the instrument package meets a sterilization standard.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 21, 2024
    Inventors: Yu-Pin Lin, Ching-Feng Lee
  • Patent number: 11991886
    Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Bo-Feng Young, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Sai-Hooi Yeong, Yu-Ming Lin
  • Publication number: 20240161797
    Abstract: An integrated circuit (IC) device includes memory cells each including first through fourth memory elements. The first memory element is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line. The second memory element is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor. The first and second memory elements are arranged in a first row along the first axis. The third memory element is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor electrically coupled to the first conductor. The fourth memory element is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line. The third and fourth memory elements are arranged, along the first axis, in a second row spaced from the first row along an axis transverse to the first axis.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Bo-Feng YOUNG, Yu-Ming LIN, Shih-Lien Linus LU, Han-Jong CHIA, Sai-Hooi YEONG, Chia-En HUANG, Yih WANG
  • Patent number: 11985906
    Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
  • Publication number: 20240147711
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
  • Patent number: 11972951
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • Patent number: 11972982
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Yu-Ming Lin, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Chandrashekhar Prakash Savant, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20240136228
    Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11966352
    Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: April 23, 2024
    Assignee: Dell Products L.P.
    Inventors: Yu-Feng Lin, Hao-Cheng Ku, Yi-Wei Lu
  • Patent number: 11961546
    Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
  • Publication number: 20240120316
    Abstract: The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.
    Type: Application
    Filed: November 17, 2022
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Kuang Ho, Yu-Jie Lin, Yi-Feng Hsu
  • Publication number: 20240120306
    Abstract: A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.
    Type: Application
    Filed: November 4, 2022
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Kuang Ho, Yu-Jie Lin, Yi-Feng Hsu