Patents by Inventor Yu-Fu Lin

Yu-Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190143457
    Abstract: A laser preheating control method is applied to a laser preheating control device. When a cutter processes a workpiece along a process path, a laser source of the device is provided to output a laser beam to the workpiece for selectively forming a laser spot on the workpiece surface. And according to a movement direction of the cutter, a laser controller of the device is provided to form the laser spot only on a preheating region of the workpiece, where in front of the cutter in the process path, for preheating the workpiece in the preheating region. As a result, the laser spot will not repeatedly heat the workpiece behind the cutter in the process path, and the qualitative change of the workpiece caused by repeating heating is preventable.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 16, 2019
    Inventors: Yu-Ting Lu, Yu-Fu Lin, Jui-Teng Chen, Wen-Long Chang, Chih-Hung Chou
  • Publication number: 20190079418
    Abstract: The present disclosure provides an exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas. The exhaust system includes: a main exhaust pipe having a top surface and a bottom surface; a first branch pipe including an upstream end coupled to a source of a gas mixture containing the hazardous gas and a downstream end connected to the main exhaust pipe through the top surface; a second branch pipe including a downstream end connected to the main exhaust pipe through the bottom surface; and a detector configured to detect presence of the hazardous gas in the second branch pipe.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Inventors: Yu-Fu Lin, Shih-Chang Shih, Chia-Chen Chen
  • Publication number: 20180364596
    Abstract: A method for creating a vacuum in a load lock chamber is provided. The method includes building an air-tight environment in the load lock chamber. The method further includes reducing the pressure in a gas tank to a predetermined vacuum pressure. The method also includes enabling an exchange of gas between the load lock chamber and the gas tank when the pressure in the gas tank is at the predetermined vacuum pressure so as to reduce the pressure in the load lock chamber to an adjusted vacuum pressure.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 20, 2018
    Inventors: Tung-Jung CHANG, Yu-Fu LIN, Sheng-Kang YU
  • Patent number: 10156794
    Abstract: Positioning devices and positioning methods are provided. The positioning device includes a laser source and an optical assembly. The optical assembly is configured to direct a laser beam projected from the laser source toward a floor and a ceiling of a semiconductor fabrication facility to generate a first laser line on the floor and a second laser line on the ceiling. The first laser line and the second laser line are parallel to and aligned with each other when viewed in a direction perpendicular to the floor and the ceiling. Accordingly, the first laser line and the second laser line can be used to align a semiconductor tool and an overhead hoist transport system in the semiconductor fabrication facility.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Kang Yu, Yu-Fu Lin, Chia-Chen Chen
  • Patent number: 9640397
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first layer is deposited over a substrate. A plurality of mandrels is formed over the first layer. Guiding-spacers are formed along sidewalls of the mandrels. Then the mandrels are removed. A neutral layer (NL) and a block copolymer (BCP) layer are deposited over the first layer and the guiding-spacers. A anneal is applied to the BCP layer to form a first polymer nanostructure between the guiding-spacers and being surrounded by a second polymer nanostructure. The first polymer nanostructures locate at a same distance from the first layer. Polymer nano-blocks are formed by selectively etching the second polymer nanostructure and the NL. By using the polymer nano-blocks and the guiding spacer as etch masks, the first layer is etched to form openings. The substrate is etched through the openings to form substrate trench and substrate fin.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh-Han Wu, Chung-Ju Lee, Tien-I Bao, Tsung-Yu Chen, Shinn-Sheng Yu, Yu-Fu Lin, Jeng-Horng Chen
  • Publication number: 20150262815
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first layer is deposited over a substrate. A plurality of mandrels is formed over the first layer. Guiding-spacers are formed along sidewalls of the mandrels. Then the mandrels are removed. A neutral layer (NL) and a block copolymer (BCP) layer are deposited over the first layer and the guiding-spacers. A anneal is applied to the BCP layer to form a first polymer nanostructure between the guiding-spacers and being surrounded by a second polymer nanostructure. The first polymer nanostructures locate at a same distance from the first layer. Polymer nano-blocks are formed by selectively etching the second polymer nanostructure and the NL. By using the polymer nano-blocks and the guiding spacer as etch masks, the first layer is etched to form openings. The substrate is etched through the openings to form substrate trench and substrate fin.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: CHIEH-HAN WU, CHUNG-JU LEE, TIEN-I BAO, TSUNG-YU CHEN, SHINN-SHENG YU, YU-FU LIN, JENG-HORNG CHEN
  • Publication number: 20150169422
    Abstract: The present invention provides an evaluation method for calibration of a processing equipment. According to the present invention, prior to processing a device, a test member including the same thickness and material with the device is manufactured. Then, the processing equipment is used to process the device, the test member and form a micro-processing structure in the test member. Next, the status of the micro-processing structure in the test member is inspected for evaluating if the processing equipment should be calibrated. In this way, the size and shape accuracy of the formation micro-processing structures using the monitored processing equipment can be reasonably guaranteed.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: FU-CHUAN HSU, YU-FU LIN, TSUNG-PIN HUNG, YU-TING LYU, ZHENG-HAN HUNG
  • Patent number: 8544317
    Abstract: A method and apparatus provide for simultaneously moving multiple semiconductor wafers in opposite directions while simultaneously performing processing operations on each of the wafers. The semiconductor wafers are orientated in coplanar fashion and are disposed on stages that simultaneously translate in opposite directions to produce a net system momentum of zero. The die of the respective semiconductor wafers are processed in the same spatial sequence with respect to a global alignment feature of the semiconductor wafer. A balance mass is not needed to counteract the motion of a stage because the opposite motions of the respective stages cancel each other.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Fu Lin, Yung-Cheng Chen, Heng-Jen Lee, Chin-Hsiang Lin
  • Patent number: 8518634
    Abstract: A method of making an integrated circuit is provided. The method includes providing a substrate having a photosensitive layer. The photosensitive layer is exposed to a radiation beam. The exposed photosensitive layer is developed in a first chamber. In the first chamber, a cleaning process is performed on the developed photosensitive layer. The cleaning process includes using a rinse solution including at least one of ozone, hydrogen peroxide, and oxalic acid.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: August 27, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsi Yeh, Yu-Fu Lin, Shao-Yen Ku, Chi-Ming Yang, Chin-Hsiang Lin
  • Publication number: 20120202156
    Abstract: A method of making an integrated circuit is provided. The method includes providing a substrate having a photosensitive layer. The photosensitive layer is exposed to a radiation beam. The exposed photosensitive layer is developed in a first chamber. In the first chamber, a cleaning process is performed on the developed photosensitive layer. The cleaning process includes using a rinse solution including at least one of ozone, hydrogen peroxide, and oxalic acid.
    Type: Application
    Filed: February 8, 2011
    Publication date: August 9, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: Ming-Hsi Yeh, Yu-Fu Lin, Shao-Yen Ku, Chi-Ming Yang, Chin-Hsiang Lin
  • Publication number: 20110083496
    Abstract: A method and apparatus provide for simultaneously moving multiple semiconductor wafers in opposite directions while simultaneously performing processing operations on each of the wafers. The semiconductor wafers are orientated in coplanar fashion and are disposed on stages that simultaneously translate in opposite directions to produce a net system momentum of zero. The die of the respective semiconductor wafers are processed in the same spatial sequence with respect to a global alignment feature of the semiconductor wafer. A balance mass is not needed to counteract the motion of a stage because the opposite motions of the respective stages cancel each other.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 14, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Fu LIN, Yung-Cheng CHEN, Heng-Jen LEE, Chin-Hsiang LIN
  • Patent number: 7098978
    Abstract: A wide-viewing angle LCD comprises a first substrate and a second substrate disposed opposite each other with a liquid crystal layer disposed therebetween. A first electrode is disposed on the interior of the first substrate. A first protrusion or slit structure with a first pattern is formed on the first electrode. A second electrode is disposed on the interior of the second substrate. A second protrusion or slit structure with a second pattern is formed on the second electrode. The first and second patterns constitute a third pattern with at least one intersection.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: August 29, 2006
    Assignee: Quanta Display Inc.
    Inventors: Chien-Hua Chen, Yu-Fu Lin, Jung-Lieh Hsu, Ruei-Liang Luo
  • Publication number: 20050219452
    Abstract: A wide-viewing angle LCD comprises a first substrate and a second substrate disposed opposite each other with a liquid crystal layer disposed therebetween. A first electrode is disposed on the interior of the first substrate. A first protrusion or slit structure with a first pattern is formed on the first electrode. A second electrode is disposed on the interior of the second substrate. A second protrusion or slit structure with a second pattern is formed on the second electrode. The first and second patterns constitute a third pattern with at least one intersection.
    Type: Application
    Filed: August 9, 2004
    Publication date: October 6, 2005
    Inventors: Chien-Hua Chen, Yu-Fu Lin, Jung-Lieh Hsu, Ruei-Liang Luo
  • Publication number: 20050200782
    Abstract: A multi-domain vertical alignment (MVA) liquid crystal display (LCD) comprising a first substrate, a second substrate and a liquid crystal layer disposed between the first substrate and the second substrate is provided. A plurality of first protrusions including a plurality of radiation-shaped protrusions arranged in stripe is formed over the first substrate. In addition, a plurality of second protrusions including stripe protrusions is formed over the second substrate. The first protrusions and the second protrusions are interlaced correspondingly. Since the radiation-shaped protrusions arranged in stripe are disposed over the first substrate, the liquid crystal molecules of the LCD may have more tilt directions. Thus, the range of the viewing angle of the LCD is increased.
    Type: Application
    Filed: January 27, 2005
    Publication date: September 15, 2005
    Inventors: Chien-Hua Chen, Yu-Fu Lin, Jung-Lieh Hsu