Patents by Inventor Yugang YANG

Yugang YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock structure for reducing power consumption on wireless mobile devices
    Patent number: 9386521
    Abstract: A mobile device (300) includes an oscillator (310) to generate a reference clock signal, a phase-locked loop (PLL) circuit (320) to generate a PLL output clock signal, a transceiver (330), a system-on-a-chip (SOC) (340) including a processor (342) and a number of other modules, and a control logic (350). The transceiver (330) generates a status control signal that indicates whether the transceiver (330) is in an active state or in an idle state. The control logic (350) receives the status control signal, and in response thereto, selectively enables/disables the PLL circuit (320), selectively routes either the reference clock signal or the PLL output clock signal to the processor (342) and/or the other modules of the SOC (340), and/or selectively routes either an idle clock signal or the PLL output clock signal to the transceiver (330).
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Tao Hu, Yugang Yang, Ting Xie, Tianyou Cai
  • CLOCK STRUCTURE FOR REDUCING POWER CONSUMPTION ON WIRELESS MOBILE DEVICES
    Publication number: 20150296452
    Abstract: A mobile device (300) includes an oscillator (310) to generate a reference clock signal, a phase-locked loop (PLL) circuit (320) to generate a PLL output clock signal, a transceiver (330), a system-on-a-chip (SOC) (340) including a processor (342) and a number of other modules, and a control logic (350). The transceiver (330) generates a status control signal that indicates whether the transceiver (330) is in an active state or in an idle state. The control logic (350) receives the status control signal, and in response thereto, selectively enables/disables the PLL circuit (320), selectively routes either the reference clock signal or the PLL output clock signal to the processor (342) and/or the other modules of the SOC (340), and/or selectively routes either an idle clock signal or the PLL output clock signal to the transceiver (330).
    Type: Application
    Filed: December 20, 2012
    Publication date: October 15, 2015
    Inventors: Tao HU, Yugang YANG, Ting XIE, Tianyou CAI