Patents by Inventor Yu Han

Yu Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240138408
    Abstract: A composition and use thereof. The composition comprises an active component a and an active component b; the active component a is a compound as shown in general formula A; and the active component b is at least one of compounds which have insecticidal, acaricidal or bactericidal activity and are different from the compound as shown in general formula A. The composition has the advantages of synergistic effect and expanding prevention and treatment spectrum, and can be used for preventing and treating various pests, particularly mite damage, and plant diseases caused by various fungi, bacteria, nematodes and viruses.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 2, 2024
    Inventors: Ning LI, Yingshuai LIU, Yingrui CUI, Xiangwei LIU, Ruibin LIU, Yunxiao SUN, Shien FAN, Yu CHEN, Baohong LIU, Jiajie NIU, Jie GAO, Ruijie FENG, Qinan HAN, Bin LI
  • Publication number: 20240142094
    Abstract: A lamp device includes a light-emitting element, a first clamping element, a second clamping element, an outer cover and a counterweight. The first clamping element is connected with the light-emitting element. The outer cover is disposed on the first clamping element. The counterweight is connected to the outer cover and is adjacent to a connection between the first clamping element and the second clamping element. When the lamp device clamps a screen, the second clamping element abuts against a back surface of the screen.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 2, 2024
    Applicant: Qisda Corporation
    Inventors: Pin-Yuan SHENG, Yu-Han CHENG, Pai-Chun CHENG
  • Publication number: 20240143529
    Abstract: A method for a host computer to access a target device via a remote extender. The target device is connected to the remote extender, and a target device driver corresponding to the target device is installed on the host computer. The method includes setting up a logic transmission pipe between the host computer and the remote extender with a network connection as the underlying transmission path, and handling an I/O request from the target device driver to access the target device via the logic transmission pipe. The method is used to allow the target device to be treated by the host computer as a local resource. Additionally, the disclosure provides a system for accessing the remote target device and a remote extender thereof.
    Type: Application
    Filed: March 9, 2023
    Publication date: May 2, 2024
    Inventors: YU-HAN LIU, SHENG-CHE CHUEH, CHONG-LI HUANG
  • Publication number: 20240139337
    Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Cheng-Hsun WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, CHUNG-YUAN MOU, Yu-Tse LEE
  • Publication number: 20240144893
    Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Inventors: JAE-HOON LEE, SEUNG-HWAN MOON, YONG-SOON LEE, YOUNG-SU KIM, CHANG-HO LEE, WHEE-WON LEE, JUN-YONG SONG, YU-HAN BAE
  • Publication number: 20240145381
    Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Patent number: 11974403
    Abstract: A method for manufacturing an electronic device includes the steps of providing a flexible substrate, forming an electric circuit layer on the flexible substrate at an elevated temperature, and enhancing a transmittance of the flexible substrate after forming the electric circuit layer.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: April 30, 2024
    Assignee: InnoLux Corporation
    Inventors: Yu-Chia Huang, Kuan-Feng Lee, Tsung-Han Tsai
  • Patent number: 11973023
    Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 11971452
    Abstract: A device and a method for nondestructively detecting a transient characteristic of a conductive screw of a turbo-generator rotor are provided. The device includes a personal computer (PC), an extremely-steep pulse generator, an ultra-high-frequency double-isolation transformer, and a pulse emitting and coupling module, which are connected in sequence. The pulse emitting and coupling module is connected to a load. A synchronous pulse receiving non-inductive divider circuit synchronously receives a characteristic waveform from the load, and the synchronous pulse receiving non-inductive divider circuit is connected to an ultra-high-speed analog/digital (A/D) module through a nonlinear saturation amplifying circuit that amplifies a signal. The PC receives a signal from the ultra-high-speed A/D module. The load includes a positive or negative excitation lead loop that is in a 180° symmetrical and instantaneous short-circuit state and a rotor shaft.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: April 30, 2024
    Assignee: HANGZHOU HENUOVA TECHNOLOGY CO., LTD.
    Inventors: Yuewu Zhang, Jianxi Liu, Yanxing Bao, Weihua Zha, Qianyi Zhang, Dongbing Liu, Weixing Yang, Xu Han, Miaoye Li, Zirui Wang, Junliang Liu, Jie Luo, Weitao Shen, Yu Fu, Han Gao
  • Patent number: 11971992
    Abstract: Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 30, 2024
    Assignee: Lattice Semiconductor Corporation
    Inventors: Fulong Zhang, Srirama Chandra, Sreepada Hegade, Joel Coplen, Wei Han, Yu Sun
  • Patent number: 11970116
    Abstract: An operating method of an optical system in a vehicle is provided. The optical system includes a display device. The display device includes a display panel and a plurality of light emitting units. The light emitting units are configured to emit a light to the display panel. The operating method includes the following steps. An emphasized portion of an object is determined. An image corresponding to the emphasized portion is displayed by the display device by adjusting a light intensity of at least a portion of the light emitted from the light emitting units.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: April 30, 2024
    Assignee: Innolux Corporation
    Inventors: Yu-Chia Huang, Tsung-Han Tsai, Kuan-Feng Lee
  • Publication number: 20240136344
    Abstract: A display device includes a substrate, at least one light emitting unit bound on the substrate, a transparency controllable unit disposed on the substrate, and an integrated circuit unit overlapped with the substrate. The integrated circuit unit includes a semiconducting structure and a conductive structure overlapped with the semiconducting structure. The integrated circuit unit is electrically connected to the at least one light emitting unit and the transparency controllable unit.
    Type: Application
    Filed: September 17, 2023
    Publication date: April 25, 2024
    Applicant: InnoLux Corporation
    Inventors: Jia-Yuan CHEN, Yu-Chia HUANG, Tsung-Han TSAI, Kuan-Feng LEE
  • Publication number: 20240137431
    Abstract: A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.
    Type: Application
    Filed: January 16, 2023
    Publication date: April 25, 2024
    Applicants: Chung Yuan Christian University, KGI Securities Co. Ltd.
    Inventors: Yu-Kuen Lai, Chao-Lin Wang, He-Ping Li, Cheng-Han Chuang, Kai-Po Chang
  • Publication number: 20240132085
    Abstract: Devices, systems, and methods for redundant braking systems and architectures are described. An example method for controlling a vehicle includes receiving, by a braking system, a first set of commands generated by a primary brake controller and a primary vehicle control unit (VCU) comprising multiple processors, receiving a second set of commands generated by the primary VCU and a secondary brake controller, receiving a third set of commands generated by a secondary VCU and the primary brake controller, receiving a fourth set of commands generated by the secondary VCU and the secondary brake controller, and selecting, based on an arbitration logic, exactly one of the first, second, third, and fourth sets of commands to operate the braking system, wherein the primary VCU and the secondary VCU are configured in a master/slave architecture.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 25, 2024
    Inventors: Yu-Ju HSU, Xiaoling HAN
  • Patent number: 11967652
    Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: April 23, 2024
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
  • Patent number: 11968848
    Abstract: An image sensor includes a first light sensor layer including light sensing cells configured to sense first light of an incident light and generate electrical signals based on the sensed first light, and a color filter array layer disposed on the first light sensor layer, and including color filters respectively facing the light sensing cells. The image sensor further includes a second light sensor layer disposed on the color filter array layer, and configured to sense second light of the incident light and generate an electrical signal based on the sensed second light. Each of the color filters includes a nanostructure including a first material having a first refractive index, and a second material having a second refractive index greater than the first refractive index, the first material and the second material being alternately disposed with a period.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: April 23, 2024
    Assignees: SAMSUNG ELECTRONICS CO., LTD., CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Seunghoon Han, Kwanghee Lee, Yongwan Jin, Yongsung Kim, Changgyun Shin, Jeongyub Lee, Amir Arbabi, Andrei Faraon, Yu Horie
  • Patent number: 11964915
    Abstract: A ceramic material includes zirconia toughened alumina (ZTA), which is doped with zinc ions and other metal ions, in which the other metal ions are chromium (Cr) ions, titanium (Ti) ions, gadolinium (Gd) ions, manganese (Mn) ions, cobalt (Co) ions, iron (Fe) ions, or a combination thereof. The ceramic material may have a hardness of 1600 Hv10 to 2200 Hv10 and a bending strength of 600 MPa to 645 MPa. The ceramic material can be used as wire bonding capillary.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: April 23, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tien-Heng Huang, Yu-Han Wu, Kuo-Chuang Chiu
  • Publication number: 20240124163
    Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 18, 2024
    Applicant: National Cheng Kung University
    Inventors: Yueh-Heng Li, Yu-Ting Wu, Chao-Wei Huang, Wei-Cheng Lo, Hsun-Chen Hsieh, Ping-Han Huang, Yi-Long Huang, Sheng-Wen Liu, Wei-Cheng Lien
  • Publication number: 20240128149
    Abstract: Some implementations described herein include systems and techniques for fabricating a semiconductor die package that includes a cooling interface region formed in surface of an integrated circuit die. The cooling interface region, which includes a combination of channel regions and pillar structures, may be directly exposed to a fluid above and/or around the semiconductor die package.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Chieh HSIEH, Wei-Kong SHENG, Ke-Han SHEN, Yu-Jen LIEN
  • Publication number: 20240128143
    Abstract: Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.
    Type: Application
    Filed: February 1, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Hsieh, Yu-Jin Hu, Hua-Wei Tseng, An-Jhih Su, Der-Chyang Yeh