Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: A flow entry aggregation method of a network system includes classifying a plurality of flow entries into a plurality of partitions according to a plurality of indicators of the plurality of flow entries, wherein each flow entry utilizes ternary strings to represent at least one field of the flow entry and the plurality of indicators are utilized to indicating network requirements corresponding to the plurality of flow entries; and utilizing bit merging or subset merging to compress the flow entries in the same partition.

Abstract: A flow entry aggregation method of a network system includes classifying a plurality of flow entries into a plurality of partitions according to a plurality of indicators of the plurality of flow entries, wherein each flow entry utilizes ternary strings to represent at least one field of the flow entry and the plurality of indicators are utilized to indicating network requirements corresponding to the plurality of flow entries; and utilizing bit merging or subset merging to compress the flow entries in the same partition.