Patents by Inventor Yu Hao

Yu Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250150962
    Abstract: Within many applications impulse radio based ultra-wideband (IR-UWB) transmission offers significant benefits for very short range high data rate communications when compared with existing standards and protocols. In many of these applications the main design goals are very low power consumption and very low complexity design for easy integration and cost reduction. Digitally programmable IR-UWB transmitters using an on-off keying modulation scheme on a 0.13 microns CMOS process operating on 1.2V supply and yielding power consumption as low as 0.9 mW at a 10 Mbps data rate with dynamic power control are enabled. The IR-UWB transmitters support new frequency hopping techniques providing more efficient spectrum usage and dynamic allocation of the spectrum when transmitting in highly congested frequency bands. Biphasic scrambling is also introduced for spectral line reduction.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: FREDERIC NABKI, DOMINIC DESLANDES, ALEXANDRE DESMARAIS, ANH-KIET VUONG, ANIS BOUNIF, WANG YU HAO, WILLIAM PHAM
  • Publication number: 20250140311
    Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: Jui-Che Tsai, Chen-Lin Yang, Yu-Hao Hsu, Shih-Lien Linus Lu
  • Publication number: 20250138619
    Abstract: An electronic device and a power saving method of the electronic device are provided. The power saving method includes following steps. A wake-up event is received in a low power consumption mode. Whether the wake-up event is an unexpected wake-up event is determined. Battery statistic data are analyzed to generate an analysis result when the wake-up event is the unexpected wake-up event. A status of a plurality of background applications operating in a background is adjusted according to the analysis result.
    Type: Application
    Filed: September 9, 2024
    Publication date: May 1, 2025
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Yi-Jing Chen, Yu-Hao Hu
  • Patent number: 12287578
    Abstract: A method of processing a substrate includes receiving a substrate including a photoresist film including exposed and unexposed portions, etching parts of the unexposed portions of the photoresist film with a developing gas in a process chamber to leave a residual part of the unexposed portions, and purging the developing gas from the process chamber with a purging gas. After purging the developing gas, the residual part of the unexposed portions is etched with the developing gas. The substrate is etched using exposed portions of the photoresist film as a mask.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: April 29, 2025
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hamed Hajibabaeinajafabadi, Akiteru Ko, Yu-Hao Tsai, Sergey Voronin
  • Publication number: 20250132268
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: December 27, 2024
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20250130379
    Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.
    Type: Application
    Filed: November 26, 2024
    Publication date: April 24, 2025
    Inventors: Yu-Hao CHEN, Hui-Yu LEE, Chung-Ming WENG, Jui-Feng KUAN, Chien-Te WU
  • Publication number: 20250116316
    Abstract: Disclosed is manual screw shaft driving device, comprising: a screw shaft, a driving member, a gripping member and a driving direction switching member, wherein the driving member is fitted around the screw shaft in a screw fit manner, the screw shaft is provided passing through a sliding and rotating space inside the gripping member, and the driving member is disposed in the sliding and rotating space, wherein while the driving direction switching member is switched to a first switching position, the screw shaft is driven to rotate only in a first rotation direction by a manual forward and backward sliding operation of the gripping member, and while the driving direction switching member is switched to a second switching position, the screw shaft is driven to rotate only in a second rotation direction by the manual forward and backward sliding operation of the gripping member.
    Type: Application
    Filed: May 8, 2024
    Publication date: April 10, 2025
    Applicant: LIN GWO TSAIR ENTERPRISE CO., LTD.
    Inventor: YU-HAO LIN
  • Patent number: 12272558
    Abstract: Selective protection and etching is provided which can be utilized in etching of a silicon containing layer with respect to a Ge or SiGe layer. In an example, the layers are stacked, and an oxide is on a side surface of the layers. A treatment is utilized to provide a modified surface or termination surface on side surfaces of the Ge/SiGe layers, and a heat treatment is provided after the gas treatment to selectively sublimate layer portions on side surfaces of the Si containing layers. The gas treatment and heat treatment are preferably in non-plasma environments. Thereafter, a plasma process is performed to form a protective layer on the Ge containing layers, and the Si containing layers can be etched with the plasma.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: April 8, 2025
    Assignee: Tokyo Electron Limited
    Inventors: Matthew Flaugh, Jonathan Hollin, Subhadeep Kal, Pingshan Luan, Hamed Hajibabaeinajafabadi, Yu-Hao Tsai, Aelan Mosden
  • Patent number: 12271029
    Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.
    Type: Grant
    Filed: May 24, 2024
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
  • Publication number: 20250110291
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a bottom package having a first sidewall and a second sidewall opposite to each other; a hybrid path layer disposed on the bottom package, wherein the hybrid path layer comprises an optical path layer and an electrical path layer, and at least one optical path of the optical path layer extends from the first sidewall of the bottom package beyond a center of the bottom package; and a plurality of dies bonded onto the hybrid path layer.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Yu-Hao Chen, Hao-Yi Tsai, An-Jhih Su, Tzuan-Horng Liu, Po-Yuan Teng, Tsung-Yuan Yu, Che-Hsiang Hsu
  • Publication number: 20250105057
    Abstract: An interconnect structure includes a first conductive feature, a first dielectric layer a first etch stop layer, a second etch stop layer, a second dielectric layer, and a second conductive feature. The first etch stop layer is disposed over the first conductive feature and the first dielectric layer. The second etch stop layer is disposed on the first etch stop layer. The second dielectric layer is disposed on the second etch stop layer. The second conductive feature includes a first conductive layer and a first barrier layer. The first conductive layer extends through the second dielectric layer, the second and the first etch stop layers to contact to the first conductive feature. The first barrier layer is sandwiched between the first conductive layer and the second dielectric layer, the first conductive layer and the second etch stop layer, and between the first conductive layer and the first etch stop layer.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Kuan Lee, Tzu-Hui Wei, Cheng-Hsiung Tsai, Chieh-Han Wu, Yu-Hao Yeh
  • Publication number: 20250104753
    Abstract: A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.
    Type: Application
    Filed: December 10, 2024
    Publication date: March 27, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien HUANG, Wei-Jer HSIEH, Yu-Hao HSU
  • Publication number: 20250093765
    Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: YU-HAO CHEN, HUI-YU LEE, JUI-FENG KUAN, CHIEN-TE WU
  • Patent number: 12254707
    Abstract: Embodiments of the present disclosure relate to a method, device and computer readable storage medium of scene text detection. In the method, a first visual representation of a first image is generated with an image encoding process. A first textual representation of a first text unit in the first image is generated with a text encoding process based on a first plurality of symbols obtained by masking a first symbol of a plurality of symbols in the first text unit. A first prediction of the masked first symbol is determined with a decoding process based on the first visual and textual representations. At least the image encoding process is updating according to at least a first training objective to increase at least similarity of the first prediction and the masked first symbol.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: March 18, 2025
    Assignees: LEMON INC., BEIJING YOUZHUJU NETWORK TECHNOLOGY CO., LTD.
    Inventors: Chuhui Xue, Wenqing Zhang, Yu Hao, Song Bai
  • Patent number: 12248637
    Abstract: The present invention discloses a method for outputting a command by detecting a movement of an object, which includes the following steps. First, an image capturing device captures images generated by the movement of the object at different timings by. Next, a motion trajectory is calculated according to the plurality of images. Further next, a corresponding command is outputted according to the motion trajectory. The present invention also provides a system which employs the above-mentioned method.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 11, 2025
    Assignee: PIXART IMAGING INCORPORATION
    Inventors: Yu-Hao Huang, Yi-Fang Lee, Ming-Tsan Kao, Nien-Tse Chen
  • Patent number: 12232972
    Abstract: Provided herein is an interspinous stabilization device, including: a central connection portion, a first side wing, a second side wing, a third side wing, and a fourth side wing. The first side wing extends from the central connection portion in a first direction. The second side wing extends from the central connection portion in the first direction. The third side wing extends from the central connection portion in a second direction opposite to the first direction. The fourth side wing extends from the central connection portion in the second direction. The central connection portion has at least one thread hole. The thread hole extends in a third direction substantially perpendicular to the first direction. The first side wing, the second side wing, the third side wing, and the fourth side wing each have a through hole.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: February 25, 2025
    Assignee: LOVE U CO., LTD
    Inventor: Yu-Hao Huang
  • Publication number: 20250054775
    Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 13, 2025
    Inventors: Ching-Yi Lin, Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen
  • Publication number: 20250052966
    Abstract: A method of forming a semiconductor package is provided. The method includes forming a micro lens recessed from the top surface of a substrate. A concave area is formed between the surface of the micro lens and the top surface of the substrate. The method includes depositing a first dielectric material that fills a portion of the concave area using a spin coating process. The method includes depositing a second dielectric material that fills the remainder of the concave area and covers the top surface of the substrate using a chemical vapor deposition process. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and over the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yi HUANG, Yu-Hao KUO, Chiao-Chun CHANG, Jui-Hsuan TSAI, Yu-Hung LIN, Shih-Peng TAI, Jih-Churng TWU, Chen-Hua YU
  • Publication number: 20250046614
    Abstract: A method of processing a substrate that includes: forming a photoresist layer including a metal and oxygen over a substrate including silicon; patterning the photoresist layer using an extreme ultraviolet (EUV) photolithographic process, a portion of the substrate being exposed after the patterning; and performing an atomic layer etching (ALE) process to etch the substrate selectively relative to the patterned photoresist layer.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Mehrdad Rostami, Yu-Hao Tsai, Toru Hisamatsu
  • Patent number: D1070730
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: April 15, 2025
    Assignee: Cheng Shin Rubber Ind. Co., Ltd.
    Inventors: Min-Chi Lin, Yu-Hao Hsu, Chen-Yang Yu, Jyun-Yi Ke, Cheng-Yu Li, Yi-Zhen Huang