Patents by Inventor Yu-Hao Hu
Yu-Hao Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126174Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Che Tu, Po-Han Wang, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11948863Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.Type: GrantFiled: February 8, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
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Patent number: 11948904Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.Type: GrantFiled: March 21, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Patent number: 11942417Abstract: A device includes a sensor die having a sensing region at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front-side redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front-side redistribution structure exposes the sensing region of the sensor die, and wherein the front-side redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization pattern on the first dielectric layer, and a second dielectric layer extending over the metallization pattern and the first dielectric layer.Type: GrantFiled: May 4, 2020Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Chi Chu, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11164508Abstract: An electronic device is disclosed. The electronic device includes a display unit, a light sensor, and a processor. The display unit has a brightness value. The light sensor senses an ambient light to generate a light intensity signal. The processor is coupled to the display unit and the light sensor and accesses a program instruction from a memory to perform the following steps: continuously receiving the light intensity signal from the light sensor; smoothing a plurality of light intensity signals to generate a plurality of smoothing signals; and maintaining the brightness value of the display unit for a preset time period and then determining whether to adjust the brightness value when a difference generated by subtracting a previous smoothing signal of a target smoothing signal of the smoothing signals from the target smoothing signal is less than the first threshold or greater than the second threshold.Type: GrantFiled: May 8, 2020Date of Patent: November 2, 2021Assignee: ASUSTEK COMPUTER INC.Inventors: Chih-Hsien Yang, Chih-Chuan Lin, Kou-Liang Lin, Chi-Liang Tsai, I-Hsi Wu, Yu-Hao Hu
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Publication number: 20200365072Abstract: An electronic device is disclosed. The electronic device includes a display unit, a light sensor, and a processor. The display unit has a brightness value. The light sensor senses an ambient light to generate a light intensity signal. The processor is coupled to the display unit and the light sensor and accesses a program instruction from a memory to perform the following steps: continuously receiving the light intensity signal from the light sensor; smoothing a plurality of light intensity signals to generate a plurality of smoothing signals; and maintaining the brightness value of the display unit for a preset time period and then determining whether to adjust the brightness value when a difference generated by subtracting a previous smoothing signal of a target smoothing signal of the smoothing signals from the target smoothing signal is less than the first threshold or greater than the second threshold.Type: ApplicationFiled: May 8, 2020Publication date: November 19, 2020Inventors: Chih-Hsien YANG, Chih-Chuan LIN, Kou-Liang LIN, Chi-Liang TSAI, I-Hsi WU, Yu-Hao HU
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Patent number: 10121520Abstract: A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.Type: GrantFiled: April 24, 2018Date of Patent: November 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Hu, Yi-Tzu Chen, Hao-I Yang, Cheng-Jen Chang, Geng-Cing Lin
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Publication number: 20180240505Abstract: A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.Type: ApplicationFiled: April 24, 2018Publication date: August 23, 2018Inventors: Yu-Hao HU, Yi-Tzu CHEN, Hao-I YANG, Cheng-Jen CHANG, Geng-Cing LIN
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Patent number: 9959911Abstract: A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.Type: GrantFiled: February 27, 2017Date of Patent: May 1, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Hu, Yi-Tzu Chen, Hao-I Yang, Cheng-Jen Chang, Geng-Cing Lin
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Patent number: 9711209Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.Type: GrantFiled: March 16, 2016Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-I Yang, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu
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Publication number: 20170169864Abstract: A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Inventors: Yu-Hao HU, Yi-Tzu CHEN, Hao-I YANG, Cheng-Jen CHANG, Geng-Cing LIN
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Patent number: 9583494Abstract: A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.Type: GrantFiled: October 23, 2013Date of Patent: February 28, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Hu, Yi-Tzu Chen, Hao-I Yang, Cheng-Jen Chang, Geng-Cing Lin
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Publication number: 20160211010Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.Type: ApplicationFiled: March 16, 2016Publication date: July 21, 2016Inventors: Hao-I YANG, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu
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Patent number: 9299391Abstract: A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.Type: GrantFiled: January 21, 2014Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-I Yang, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu
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Publication number: 20150206555Abstract: A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.Type: ApplicationFiled: January 21, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-I YANG, Yi-Tzu CHEN, Cheng-Jen CHANG, Geng-Cing LIN, Yu-Hao HU
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Publication number: 20150109847Abstract: A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.Type: ApplicationFiled: October 23, 2013Publication date: April 23, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hao HU, Yi-Tzu CHEN, Hao-I YANG, Cheng-Jen CHANG, Geng-Cing LIN
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Patent number: 8958237Abstract: An apparatus and method for executing a write operation in a static random access memory (SRAM) array including memory cells that are coupled to a plurality of word lines and to a plurality of bit lines are provided. A clock signal is generated to start a write operation. A pulse is generated on the plurality of word lines in response to the clock signal. An operation voltage of the SRAM array is lowered for a period of time during the write operation. The period of time is controlled and the pulse is ended using a tracking circuit. The tracking circuit includes a plurality of tracking memory cells. The plurality of tracking memory cells have a timing characteristic that emulates a timing characteristic of the SRAM array during the write operation. The tracking circuit controls the period of time and ends the pulse based on the emulated timing characteristic.Type: GrantFiled: November 13, 2013Date of Patent: February 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hao-I Yang, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu, Chia-Hao Hsu
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Patent number: 8837207Abstract: A static memory and a static memory cell are provided. The static memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first switch, a second switch, a third switch, a first pull-down switch, and a second pull-down switch. When a data writing operation is performed, the latching capability of the latch circuit constituted by the first to the sixth transistors is disabled by turning off the second transistor or the fifth transistor, so that the speed of the data writing operation is increased and the data writing performance is improved. The first switch and the second switch provide a path for reading or writing data, and the third switch is coupled to a bit line for receiving data from or transmitting data to the bit line.Type: GrantFiled: October 9, 2013Date of Patent: September 16, 2014Assignee: National Chiao Tung UniversityInventors: Shyh-Jye Jou, Ming-Hsien Tu, Yu-Hao Hu, Ching-Te Chuang, Yi-Wei Chiu