Patents by Inventor Yu-Hao Kuo

Yu-Hao Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446521
    Abstract: In accordance with some embodiments of the present disclosure, an integrated fan-out (INFO) package includes a substrate, a molding compound, a buffer layer, a first chip, a second chip, and a redistribution circuit structure layer. The molding compound is disposed on the substrate. The buffer layer is disposed on the substrate and includes a first buffer pattern and a second pattern separated from the first buffer pattern by a distance. A thickness of the first buffer pattern is greater than a thickness of the second buffer pattern. The first chip is attached to the substrate through the first buffer pattern and surrounded by the molding compound. The second chip is attached to the substrate through the second buffer pattern and surrounded by the molding compound. The redistribution circuit structure layer is disposed on the molding compound and electrically connected to the first chip and the second chip.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20190312004
    Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Publication number: 20190295971
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10410684
    Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: September 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu
  • Publication number: 20190266708
    Abstract: A method for removing haze from an image is provided. The image is converted to S(x) and V(x), the S(X) is saturation component of the image, and the V(x) is value component of the image. The S(x) is filtered to obtain S?(x), and the V(x) is filtered to obtain V?(x). A depth d(x) is estimated by calculating a difference between the S?(x) and V?(x). Once a transmission map t(x) is calculated based on the d(x), haze is removed from the image based on the transmission map t(x).
    Type: Application
    Filed: February 22, 2019
    Publication date: August 29, 2019
    Inventors: CHUN-HSIANG HUANG, TING-HAO CHUNG, CHUN-YI WANG, YU-FENG KUO
  • Publication number: 20190237423
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, an encapsulant, a first RDL structure, and a conductive terminal. The encapsulant is aside the first die, encapsulating sidewalls of the first die. The first RDL structure is on the first die and the encapsulant. The conductive terminal is electrically connected to first die through the RDL structure. The first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 10366966
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Publication number: 20190225486
    Abstract: A method for manufacturing a MEMS device includes disposing at least one bonding portion having a smaller bonding area in a region where an airtight chamber will be formed, and disposing a metal getter on a bonding surface of the bonding portion. According to this structure, when substrates are bonded to define the airtight chamber, the metal getter is squeezed out of the bonding position due to the larger bonding pressure of the bonding portion with a smaller bonding area. Then, the metal getter is activated to absorb the moisture in the airtight chamber. According to the above process, no additional procedure is needed to remove the moisture in the airtight chamber. A MEMS device manufactured by the above manufacturing method is also disclosed.
    Type: Application
    Filed: May 16, 2018
    Publication date: July 25, 2019
    Inventors: Yu-Hao CHIEN, Li-Tien TSENG, Chih-Liang KUO
  • Publication number: 20190221639
    Abstract: A method for fabrication a nanosheet device includes providing forming a stacked layer on a substrate, having first material layers and second material layers in different materials, alternatingly stacked up. The stacked layer is patterned to a stacked fin. A dummy stack is formed on the stacked fin. An etching back process is performed with the dummy stack with spacers to etch the stacked fin and expose the substrate. Laterally etches the first material layers and the second material layers, to have indent portions. Inner spacers fill the indent portions. A first/second source/drain layer is formed on the substrate at both sides of the dummy stack. Etching process is performed to remove the dummy gate of the dummy stack and the selected one of the first material layers and the second material layers between the inner spacers. Metal layer fills between the spacers and the inner spacers.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Kuan-Hao Tseng, Yu-Hsiang Lin, Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Chueh-Fei Tai, Cheng-Ping Kuo
  • Publication number: 20190221238
    Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.
    Type: Application
    Filed: February 21, 2018
    Publication date: July 18, 2019
    Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu
  • Publication number: 20190212773
    Abstract: The application discloses a support device, mounted in a portable electronic device, including an upper-cover shell, a base shell, and a pivot. The support device includes a cam structure, a first rod member, a second rod member, and a support member. The cam structure is connected to the pivot. The first pivot portion and the second pivot are pivotally connected to the base shell. The first rod member is in contact with the cam structure, and includes a first slide portion. The second rod member includes a second slide portion, movably connected to the first slide portion. The support member penetrates through an opening of the base shell, where a top surface of the support member and the second rod member are in contact with each other.
    Type: Application
    Filed: November 30, 2018
    Publication date: July 11, 2019
    Inventors: Cheng-Shi JIANG, Yen-Chi KUO, Tzu-Ming YANG, Yu-Hao CHIU, Yu-Shu ZHENG, Jeng-Hong CHIU, Chih-Ming CHEN, Chih-Liang CHIANG
  • Patent number: 10333259
    Abstract: A power distribution unit comprising at least two conductors, a plurality of outlets, a plurality of indicator lights, an AC-DC conversion circuit, and a control circuit is provided. Each outlet is electrically coupled to two of the conductors. Each indicator light corresponds to one of the outlets. The input of the AC-DC conversion circuit is electrically coupled to two of the conductors. The control circuit is electrically coupled to the indicator lights and the output of the AC-DC conversion circuit. The control circuit is configured for sequentially driving the indicator lights, and is configured for controlling, according to the group information of each grouped outlet, a corresponding indicator light to display a corresponding color of a group to which the grouped outlet belongs.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: June 25, 2019
    Assignee: CYBER POWER SYSTEMS, INC.
    Inventors: Yu-Chen Kuo, Yung-Hao Peng, Wen-Pin Lai
  • Patent number: 10332856
    Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Patent number: 10319691
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10304700
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Shih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20190157121
    Abstract: A polyimide composition for a package structure is provided. The polyimide composition includes a polyimide precursor, a cross-linker, a photosensitizer, a first additive, a second additive and a solvent. The first additive comprises a polyether based compound, and the second additive comprises a siloxane based compound. The polyimide composition has more than 98% cyclization of the polyimide precursor when the polyimide composition is cured at a temperature range of 160° C. to 200° C.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sih-Hao Liao, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10296278
    Abstract: A PDA (power distribution apparatus) having capability for color management has at least one PDU (power distribution unit). The PDU has a plurality of outlets and a display; wherein the screen color of the display can display different colors according to the management item, thereby enhancing visualization of the management of the PDA.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 21, 2019
    Assignee: CYBER POWER SYSTEMS, INC.
    Inventors: Yu-Chen Kuo, Yung-Hao Peng, Shih-Chien Tang
  • Publication number: 20190140068
    Abstract: A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Cheng-Ping Kuo, Kuan-Hao Tseng
  • Publication number: 20190139924
    Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Publication number: 20190139937
    Abstract: In accordance with some embodiments of the present disclosure, an integrated fan-out (INFO) package includes a substrate, a molding compound, a buffer layer, a first chip, a second chip, and a redistribution circuit structure layer. The molding compound is disposed on the substrate. The buffer layer is disposed on the substrate and includes a first buffer pattern and a second pattern separated from the first buffer pattern by a distance. A thickness of the first buffer pattern is greater than a thickness of the second buffer pattern. The first chip is attached to the substrate through the first buffer pattern and surrounded by the molding compound. The second chip is attached to the substrate through the second buffer pattern and surrounded by the molding compound. The redistribution circuit structure layer is disposed on the molding compound and electrically connected to the first chip and the second chip.
    Type: Application
    Filed: December 19, 2017
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao