Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.

Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. The die has a front surface and a back surface opposite to the front surface. The underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. The patterned dielectric layer is disposed on the back surface of the die. The conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.

Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.

Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.

Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.

Abstract: A method for driving an electronic device includes the following steps: receiving a first image data, detecting a first frame rate corresponding to the first image data, generating at least one first scanning signal according to the first image data, receiving a second image data, detecting a second frame rate corresponding to the second image data, and generating at least one second scanning signal according to the second image data. The at least one first scanning signal has a first high voltage level value. The at least one second scanning signal has a second high voltage level value. When the first frame rate is different from the second frame rate, the first high voltage level value is different from the second high voltage level value.

Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.

Abstract: A device includes a sensor die having a sensing region at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front-side redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front-side redistribution structure exposes the sensing region of the sensor die, and wherein the front-side redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization pattern on the first dielectric layer, and a second dielectric layer extending over the metallization pattern and the first dielectric layer.

Abstract: A backlight module and an electronic device are provided. The backlight module, having a main region and a peripheral region near the main region, includes a light conversion layer, multiple light conversion patterns located in the peripheral region, and multiple light emitting units emitting a light beam. A first portion and a second portion of the light beam emitted respectively from the main region and the peripheral region both have at least one corresponding position in a CIE 1931 color space. One among the at least one corresponding position of the first portion of the light beam has corresponding coordinates (x1, y1). One among the at least one corresponding position of the second portion of the light beam has corresponding coordinates (x2, y2). The corresponding coordinates (x1, y1) and the corresponding coordinates (x2, y2) satisfy the following relation: 0?|x1?x2|?0.2.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.

Abstract: An optical component includes a phase diffraction grating and an amplitude diffraction grating. The phase diffraction grating includes a center concave section and a plurality of ring stages. The ring stages surround the center concave section. The center concave section and the ring stages form a cavity, where a light source is disposed in the cavity and emits the light to the optical component. Each of the ring stages has a stage surface. Each of the stage surfaces includes a plurality of ring microstructures arranged in concentric circles. The widths of each ring microstructure in at least one of the ring stages are less than the quarter wavelength of the light. The amplitude diffraction grating includes a center convex section and a plurality of ring parts. The center convex section and the center concave section are aligned. The ring parts surround the central convex section.

Abstract: A boot up method makes an electronic system boot up by a processor according to a boot code in a NAND flash memory and includes the following steps. First, the flash memory storing a boot code or boot codes is provided. Next, a first boot code is copied to an XIP memory in response to a hardware reset signal. Then, the processor executes the first boot code in the XIP memory and thus makes the system boot up. Next, whether the system boots up successfully is judged after a time delay. When the system fails to boot up, the system is reset and a second boot code is copied to the XIP memory. Thereafter, the processor executes the second boot code in the XIP memory and thus boots up the system. If the system still fails to boot up, the above-mentioned steps are repeated until the system boots up successfully.

Abstract: A boot up method makes an electronic system boot up by a processor according to a boot code in a NAND flash memory and includes the following steps. First, the flash memory storing a boot code or boot codes is provided. Next, a first boot code is copied to an XIP memory in response to a hardware reset signal. Then, the processor executes the first boot code in the XIP memory and thus makes the system boot up. Next, whether the system boots up successfully is judged after a time delay. When the system fails to boot up, the system is reset and a second boot code is copied to the XIP memory. Thereafter, the processor executes the second boot code in the XIP memory and thus boots up the system. If the system still fails to boot up, the above-mentioned steps are repeated until the system boots up successfully.