Patents by Inventor Yu-Hao SU

Yu-Hao SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152193
    Abstract: The invention provides a power supply including at least one power output port, at least one status alert component, and at least one output port status monitoring module. The status alert component generates at least one visual prompt based on an alert signal. The output port status monitoring module includes at least one temperature sensor adjacent to the power output port, a microcontroller connected to the temperature sensor and sensing an output current from the power output port, and a reset signal generator connected to the microcontroller. The microcontroller comprises at least one port status alert condition that takes a temperature and the output current of the power output port as decision factors. The microcontroller outputs the alert signal to the status alert component when the port status alert condition is met and maintains the status until a reset signal provided by the reset signal generator is received.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Inventors: Wei-Chen WU, Wen-Hau HU, Hung-Wei YANG, Cheng-Yung LO, Yu-Hao SU, Jian-Zhi HUANG
  • Patent number: 9548265
    Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: January 17, 2017
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Shu-Ming Chang, Hsing-Lung Shen, Yu-Hao Su, Kuan-Jung Wu, Yi Cheng
  • Publication number: 20160315043
    Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.
    Type: Application
    Filed: April 25, 2016
    Publication date: October 27, 2016
    Inventors: Yen-Shih HO, Shu-Ming CHANG, Hsing-Lung SHEN, Yu-Hao SU, Kuan-Jung WU, Yi CHENG
  • Publication number: 20160315048
    Abstract: A semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The conducting ring has at least two connecting points. The wafer has a first surface and an opposite second surface. An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.
    Type: Application
    Filed: April 25, 2016
    Publication date: October 27, 2016
    Inventors: Yen-Shih HO, Shu-Ming CHANG, Hsing-Lung SHEN, Yu-Hao SU, Kuan-Jung WU, Yi CHENG