Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A silicon photonic platform includes a composite substrate with a first photonic platform layer which includes a photonic platform material. A first signal layer covers the first photonic platform layer, has a top surface, and includes the photonic platform material and a first signal material. A photonic platform spectral signal is different from the first signal material spectral signal. The second photonic platform layer has a top surface, covers at least a portion of the top surface of the first signal, and includes the photonic platform material. The second photonic platform layer includes at least one ridge structure, and forms a silicon photonic platform together with the first photonic platform layer.

Abstract: The disclosure provides an electronic device including a substrate, two adjacent first lines, an electrode, and a light shielding structure. The two adjacent first lines disposed on the substrate and extending along a first direction. The electrode disposed on the substrate. The light shielding structure disposed on the substrate and defined an opening. In a top view of the electronic device, at least a portion of the electrode is overlapped with the opening, the opening includes a first side, a second side, and a third side, the second side connects the first side and the third side, the first side and the third side are extending along a second direction perpendicular to the first direction, the second side has at least one straight line segment, and an acute angle is between an extension direction of the at least one straight line segment and the first direction.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: Selective protection and etching is provided which can be utilized in etching of a silicon containing layer with respect to a Ge or SiGe layer. In an example, the layers are stacked, and an oxide is on a side surface of the layers. A treatment is utilized to provide a modified surface or termination surface on side surfaces of the Ge/SiGe layers, and a heat treatment is provided after the gas treatment to selectively sublimate layer portions on side surfaces of the Si containing layers. The gas treatment and heat treatment are preferably in non-plasma environments. Thereafter, a plasma process is performed to form a protective layer on the Ge containing layers, and the Si containing layers can be etched with the plasma.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a bottom package having a first sidewall and a second sidewall opposite to each other; a hybrid path layer disposed on the bottom package, wherein the hybrid path layer comprises an optical path layer and an electrical path layer, and at least one optical path of the optical path layer extends from the first sidewall of the bottom package beyond a center of the bottom package; and a plurality of dies bonded onto the hybrid path layer.

Abstract: A display device having a general display region and a camera display region is provided. The general display region includes a first region, and the camera display region includes a second region. The display device includes a plurality of data lines and a plurality of gate lines. An area of the first region is defined by two adjacent ones of the plurality of data lines and two adjacent ones of the plurality of gate lines. An area of the second region is defined by another two adjacent ones of the plurality of data lines and another two adjacent ones of the plurality of gate lines. The area of the second region is greater than the area of the first region.

Abstract: An interconnect structure includes a first conductive feature, a first dielectric layer a first etch stop layer, a second etch stop layer, a second dielectric layer, and a second conductive feature. The first etch stop layer is disposed over the first conductive feature and the first dielectric layer. The second etch stop layer is disposed on the first etch stop layer. The second dielectric layer is disposed on the second etch stop layer. The second conductive feature includes a first conductive layer and a first barrier layer. The first conductive layer extends through the second dielectric layer, the second and the first etch stop layers to contact to the first conductive feature. The first barrier layer is sandwiched between the first conductive layer and the second dielectric layer, the first conductive layer and the second etch stop layer, and between the first conductive layer and the first etch stop layer.

Abstract: A method for a base station (BS) instructing a UE to monitor a physical downlink control channel (PDCCH) for power saving signaling is disclosed. The method comprises transmitting a discontinuous reception (DRX) configuration to the UE indicating to monitor a scheduling signal on the PDCCH within a DRX active time, and transmitting a configuration to the UE for monitoring the power saving signaling on the PDCCH, instructing the UE to wake up for monitoring the scheduling signal in the DRX active time, wherein the configuration includes a time in milliseconds prior to a start of a DRX on-duration time, and instructs the UE to start monitoring the PDCCH for the power saving signaling.

Abstract: A photonic integrated circuit structure includes a semiconductor substrate. A waveguide is disposed above the semiconductor substrate and has an inclined plane. A mirror coating layer is conformally disposed on the inclined plane. A cladding layer covers the waveguide and the mirror coating layer. A hole is disposed in the semiconductor substrate or the cladding layer, and the hole overlaps the inclined plane in a vertical direction. In addition, an optical fiber is disposed in the hole to receive a reflected light from the mirror coating layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Abstract: Impurities in a liquefied solid fuel utilized in a droplet generator of an extreme ultraviolet photolithography system are removed from vessels containing the liquefied solid fuel. Removal of the impurities increases the stability and predictability of droplet formation which positively impacts wafer yield and droplet generator lifetime.

Abstract: A method of forming a semiconductor package is provided. The method includes forming a micro lens recessed from the top surface of a substrate. A concave area is formed between the surface of the micro lens and the top surface of the substrate. The method includes depositing a first dielectric material that fills a portion of the concave area using a spin coating process. The method includes depositing a second dielectric material that fills the remainder of the concave area and covers the top surface of the substrate using a chemical vapor deposition process. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and over the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.

Abstract: A method of processing a substrate that includes: forming a photoresist layer including a metal and oxygen over a substrate including silicon; patterning the photoresist layer using an extreme ultraviolet (EUV) photolithographic process, a portion of the substrate being exposed after the patterning; and performing an atomic layer etching (ALE) process to etch the substrate selectively relative to the patterned photoresist layer.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: The present invention disclose a medical image-based system for predicting lesion classification and a method thereof. The system comprises a feature data extracting module for providing a raw feature data based on a medical image, and a predicting module for outputting a predicted class and a risk index according to the raw feature data. The predicting module comprises a classification unit for generating the predicted class and a prediction score corresponding thereto according to the raw feature data, and a risk evaluation unit for generating the risk index according to the prediction score. The system provides medical personnels a reference score and a risk index to determine progression of a certain disease.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: The disclosure provides an electronic device including a substrate, two adjacent first lines, two adjacent second lines and an opening. Two adjacent first lines extending along a first direction, two adjacent first lines and two disposed adjacent second lines are disposed on the substrate. The pixel is defined by the two adjacent first lines and the two adjacent second lines. The opening is corresponding to the pixel, and an edge of the opening is adjacent to an edge of one of the two adjacent first lines. A distance between the edge of the opening and the edge of the one of the two adjacent first lines is from 1 micrometer to 2 micrometers. The opening comprises a first arc portion and a second arc portion, and the first arc portion and the second arc portion are disposed at diagonal corners of the opening.

Abstract: A method for processing a substrate that includes: performing a cyclic process including a plurality of cycles, where the cyclic process includes, forming a carbon-containing layer over sidewalls of a recess in a Si-containing dielectric layer of the substrate, the forming including exposing the substrate disposed in a plasma processing chamber to a first plasma generated from a first gas including carbon and hydrogen, modifying a surface of the carbon-containing layer by exposing the substrate to a second plasma generated from a second gas including oxygen, and forming a passivation layer over the modified surface of the carbon-containing layer by exposing the substrate to a third gas including B, Si, or Al.

Abstract: Embodiments of improved processes and methods that provide selective etching of silicon nitride are disclosed herein. More specifically, a cyclic, two-step dry etch process is provided to selectively etch silicon nitride layers formed on a substrate, while protecting oxide layers formed on the same substrate. The cyclic, two-step dry etch process sequentially exposes the substrate to: (1) a hydrogen plasma to modify exposed surfaces of the silicon nitride layer and the oxide layer to form a modified silicon nitride surface layer and a modified oxide surface layer, and (2) a halogen plasma to selectively etch silicon nitride by removing the modified silicon nitride surface layer without removing the modified oxide surface layer. The oxide layer is protected from etching during the removal step (i.e., step 2) by creating a crystallized water layer on the oxide layer during the surface modification step (i.e., step 1).