Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

Abstract: A method for forming a dielectric layer of a semiconductor is described. At first, providing a substrate with a metal-conductive layer having been formed thereon. Next covering the substrate with a membrane having a plurality of micro-holes. Afterward spraying a fluid dielectric on the membrane having a plurality of micro-holes. After waiting a period of time for the gaps among the metal conductors being filled with the fluid dielectric, removing the membrane having a plurality of micro-holes from the substrate. Further baking the substrate to cure the fluid dielectric inside metal-conductive layer. The thickness of the dielectric after curing is approximately equal to the thickness of the metal-conductive layer. At last forming a cap dielectric layer on the substrate.

Abstract: A process for making split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an interpoly dielectric layer.

Abstract: A MOS transistor with a pair of lightly doped drain (LDD) sub-regions in the substrate and whose gate electrode is self-aligned with a non-doped gate oxide layer overlying the channel region between the two LDD sub-regions.

Abstract: A method of manufacturing an electron tunnel oxide (ETOX) flash memory device having an improved coupling efficiency includes sequentially forming a tunnel oxide, a floating gate, a dielectric layer, and a control gate on a substrate, where the tunnel oxide and the bottom of the floating gate are formed to be narrower than the top of the floating gate, the dielectric and the control gate.

Abstract: A split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an inter-poly dielectric layer.

Abstract: A structure of dynamic random access memory includes a field effect transistor (FET), a capacitor, a world line and a bit line. The gate of the FET is electrically coupled to the word line in which a voltage source is supplied through the world line to the gate. The drain region of the FET is electrically coupled to a lower electrode of the capacitor. The capacitor has an upper electrode being electrically coupled to the gate of the FET either. The source region of the FET is electrically coupled to the bit line.

Abstract: A MOS device is provided with a reduced source and drain area. This is accomplished by first providing a MOS device with a buried gate region. The buried gate region is located on top of a channel region, which runs horizontally along the bottom of the gate trench. The source and drain regions are aligned vertically an parallel to the outside sidewalls of the buried gate region. Sidewall protectors are provided between the gate and lateral source and drain regions on the inside sidewalls of the gate trench. Additionally, a process for manufacturing the above described device is also disclosed.

Abstract: A method of forming local interconnection of a SRAM, including the following steps: First, an NMOS and a PMOS are formed on a P-well and an N-well on a substrate, respectively. An isolation oxide layer is formed and the isolation oxide layer on a node is removed. A thin polysilicon layer is formed and N+ shallow implantation and N+ deep implantation is performed by using a photolithography technique. Also, P+ shallow implantation and P+ deep implantation are performed by using a photolithography technique. After the formation of a low resistance material, the low resistance material and the thin polysilicon layer are together formed.