Patents by Inventor Yu-Hao Yang
Yu-Hao Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996468Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.Type: GrantFiled: September 2, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chih Lin, Hsiu-Hao Tsao, Szu-Chi Yang, Shih-Hao Lin, Yu-Jiun Peng, Chang-Jhih Syu, An Chyi Wei
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Patent number: 11993863Abstract: A metal product includes a metal substrate, at least one first hole, at least one second hole, and at least one third hole. The first hole is formed in a surface of the metal substrate. The second hole is formed in at least one of a portion of the surface of the metal substrate without the first hole and an inner surface defining the first hole. The third hole is formed in at least one of a portion of the surface of the metal substrate without the first hole and without the second hole, a portion of the inner surface defining the first hole without the second hole, and an inner surface defining the second hole. The first, second, and third holes enhance a bonding strength between the metal product and a material product. The disclosure also provides a metal composite and a method for manufacturing the metal product.Type: GrantFiled: September 24, 2021Date of Patent: May 28, 2024Assignee: Fulian Yuzhan Precision Technology Co., LtdInventors: Yu-Mei Hu, Shi-Chu Xue, Li-Ming Shen, Zheng-Quan Wang, Dong-Xu Zhang, Zhong-Hua Mai, An-Li Qin, Qing-Rui Wang, Ching-Hao Yang, Kar-Wai Hon, Hao Zhou
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Publication number: 20240152193Abstract: The invention provides a power supply including at least one power output port, at least one status alert component, and at least one output port status monitoring module. The status alert component generates at least one visual prompt based on an alert signal. The output port status monitoring module includes at least one temperature sensor adjacent to the power output port, a microcontroller connected to the temperature sensor and sensing an output current from the power output port, and a reset signal generator connected to the microcontroller. The microcontroller comprises at least one port status alert condition that takes a temperature and the output current of the power output port as decision factors. The microcontroller outputs the alert signal to the status alert component when the port status alert condition is met and maintains the status until a reset signal provided by the reset signal generator is received.Type: ApplicationFiled: November 4, 2022Publication date: May 9, 2024Inventors: Wei-Chen WU, Wen-Hau HU, Hung-Wei YANG, Cheng-Yung LO, Yu-Hao SU, Jian-Zhi HUANG
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Patent number: 11980016Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.Type: GrantFiled: July 20, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
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Publication number: 20240119875Abstract: A mending method for a display includes the steps of making a display device light to make a plurality of light emitting positions thereof shine, searching out a plurality of defect positions among the light emitting positions, providing a transferring device having a transferring surface with a plurality of miniature light emitting elements positioned correspondingly to the light emitting positions, planning a mending procedure which includes in the area the transferring surface corresponds to, choosing in chief the largest number of defect positions able to be mended at a single time according to the positions of the miniature light emitting elements and then in the area the transferring surface corresponds to, planning the rest of the defect positions according to the rest of the miniature light emitting elements, and according to the mending procedure, moving the transferring device to weld the miniature light emitting elements at the defect positions.Type: ApplicationFiled: October 5, 2023Publication date: April 11, 2024Inventors: Tsan-Jen CHEN, Chih-Hao TSAI, Yu-Cheng YANG, Jen-Hung Lo, Yan-Ru TSAI
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Publication number: 20240084445Abstract: A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.Type: ApplicationFiled: January 4, 2023Publication date: March 14, 2024Inventors: Chih-Wei Chou, Yuan-Hsin Chi, Chih-Hao Yang, Hung-Chih Wang, Yu-Chi Liu, Sheng-Yuan Lin
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Publication number: 20040253837Abstract: A method for forming a dielectric layer of a semiconductor is described. At first, providing a substrate with a metal-conductive layer having been formed thereon. Next covering the substrate with a membrane having a plurality of micro-holes. Afterward spraying a fluid dielectric on the membrane having a plurality of micro-holes. After waiting a period of time for the gaps among the metal conductors being filled with the fluid dielectric, removing the membrane having a plurality of micro-holes from the substrate. Further baking the substrate to cure the fluid dielectric inside metal-conductive layer. The thickness of the dielectric after curing is approximately equal to the thickness of the metal-conductive layer. At last forming a cap dielectric layer on the substrate.Type: ApplicationFiled: June 10, 2003Publication date: December 16, 2004Inventor: Yu-Hao Yang
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Patent number: 6329248Abstract: A process for making split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an interpoly dielectric layer.Type: GrantFiled: March 20, 2000Date of Patent: December 11, 2001Assignee: Winbond Electronics CorpInventor: Yu-Hao Yang
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Patent number: 6155537Abstract: A MOS transistor with a pair of lightly doped drain (LDD) sub-regions in the substrate and whose gate electrode is self-aligned with a non-doped gate oxide layer overlying the channel region between the two LDD sub-regions.Type: GrantFiled: July 9, 1998Date of Patent: December 5, 2000Assignee: Windbond Electronics Corp.Inventor: Yu-Hao Yang
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Patent number: 6153904Abstract: A method of manufacturing an electron tunnel oxide (ETOX) flash memory device having an improved coupling efficiency includes sequentially forming a tunnel oxide, a floating gate, a dielectric layer, and a control gate on a substrate, where the tunnel oxide and the bottom of the floating gate are formed to be narrower than the top of the floating gate, the dielectric and the control gate.Type: GrantFiled: December 4, 1998Date of Patent: November 28, 2000Assignee: Winbond Electronics CorporationInventor: Yu-Hao Yang
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Patent number: 6093945Abstract: A split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an inter-poly dielectric layer.Type: GrantFiled: July 9, 1998Date of Patent: July 25, 2000Assignee: Windbond Electronics Corp.Inventor: Yu-Hao Yang
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Patent number: 6040595Abstract: A structure of dynamic random access memory includes a field effect transistor (FET), a capacitor, a world line and a bit line. The gate of the FET is electrically coupled to the word line in which a voltage source is supplied through the world line to the gate. The drain region of the FET is electrically coupled to a lower electrode of the capacitor. The capacitor has an upper electrode being electrically coupled to the gate of the FET either. The source region of the FET is electrically coupled to the bit line.Type: GrantFiled: May 15, 1998Date of Patent: March 21, 2000Assignee: Winbond Electronics Corp.Inventor: Yu-Hao Yang
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Patent number: 6037231Abstract: A MOS device is provided with a reduced source and drain area. This is accomplished by first providing a MOS device with a buried gate region. The buried gate region is located on top of a channel region, which runs horizontally along the bottom of the gate trench. The source and drain regions are aligned vertically an parallel to the outside sidewalls of the buried gate region. Sidewall protectors are provided between the gate and lateral source and drain regions on the inside sidewalls of the gate trench. Additionally, a process for manufacturing the above described device is also disclosed.Type: GrantFiled: November 21, 1997Date of Patent: March 14, 2000Assignee: Winbond Electronics CorporationInventor: Yu-Hao Yang
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Patent number: 5979784Abstract: A method of forming local interconnection of a SRAM, including the following steps: First, an NMOS and a PMOS are formed on a P-well and an N-well on a substrate, respectively. An isolation oxide layer is formed and the isolation oxide layer on a node is removed. A thin polysilicon layer is formed and N+ shallow implantation and N+ deep implantation is performed by using a photolithography technique. Also, P+ shallow implantation and P+ deep implantation are performed by using a photolithography technique. After the formation of a low resistance material, the low resistance material and the thin polysilicon layer are together formed.Type: GrantFiled: April 17, 1997Date of Patent: November 9, 1999Assignee: Winbond Electronics Corp.Inventors: Kuei-Chang Liang, Yu-Hao Yang