Abstract: A probe head includes multiple probes and guide plates. Each probe includes a first end, a second end, and a probe body. The first end abuts a contact pad of a device under test. The second end abuts a contact pad of a board of a probe system. The probe body extends between the first end and the second end according to a longitudinal development axis. The guide plate includes a guide-hole pair for a probe pair of the probe head to respectively pass through, and the guide-hole pair slidably accommodate the pair of probes. The guide plate further includes an extension hole extending from one guide hole of the guide-hole pair to another guide hole. The extension hole intersects with at least one of the first guide holes and is located substantially between the probe pair on the first guide plate.

Abstract: A probe system and a probe card, a probe head and a guide plate structure thereof are described herein. The probe head includes a plurality of probes and guide plates. Each probe includes a first end, a second end, and a probe body. The first end is configured to abut a contact pad of the device under test. The second end is configured to abut a contact pad of a board of the probe system. The probe body extends between the first end and the second end according to a longitudinal development axis. The guide plate includes a pair of first guide holes for a pair of probes to pass through, and the pair of first guide holes are configured to slidably accommodate the pair of probes. The material between the pair of first guide holes in the guide plate has a relative dielectric constant not greater than 6, so as to reduce the return loss between the probe head and the device under test.

Abstract: A probe head includes multiple probes and guide plates. Each probe includes a first end, a second end, and a probe body. The first end abuts a contact pad of a device under test. The second end abuts a contact pad of a board of a probe system. The probe body extends between the first end and the second end according to a longitudinal development axis. The guide plate includes a guide-hole pair for a probe pair of the probe head to respectively pass through, and the guide-hole pair slidably accommodate the pair of probes. The guide plate further includes an extension hole extending from one guide hole of the guide-hole pair to another guide hole to provide compensating impedance between the guide-hole pair, improve impedance matching when probing the device under test with the probe pair, and reduce return loss between the probe head and the device under test.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

Abstract: The present invention relates to novel antimicrobial peptides and compositions comprising the same. The present invention also provides a method for for treating microbial infections, including bacterial infections and fungal infections.

Abstract: The present disclosure generally provides an apparatus and method for gas diffuser support structure for a vacuum chamber. The gas diffuser support structure comprises a backing plate having a central bore, and a gas deflector having a length and a width unequal to the length coupled to the backing plate by a plurality of outward fasteners coupled to a plurality of outward threaded holes formed in the backing plate, in which a spacer is disposed between the backing plate and the gas deflector, and in which a length to width ratio of the gas deflector is about 0.1:1 to about 10:1.

Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.

Abstract: A packaging method, includes: providing a continuous multi-package structure, which includes a lead frame and a molding layer formed on the lead frame, wherein the lead frame includes a plurality of recesses formed on a bottom surface on a side of the lead frame opposite to the molding layer; forming a coating layer on the bottom surface, to cover the bottom surface and the recesses on the bottom surface; and mechanically cutting the continuous multi-package structure through the recesses, to separately form a plurality of packaging units, wherein in each of the packaging units, an exposed portion of the lead frame exposed in the recesses includes a step shape.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: The present disclosure provides a latch mechanism, applied to a rack-mount server system. The rack-mount server system includes a server and a manifold, and the server includes a casing and a fluid connector. The manifold includes a manifold connector. The latch mechanism includes a fixing member, a fixing frame and a hook member. The fixing member is disposed on the manifold and includes a fixing pin. The fixing frame is secured to the server and includes a shaft. The hook member is rotatably disposed on the shaft and includes a hook portion. By rotating the hook portion to latch with the fixing pin, the fixing frame and fixing member are secured with each other, and the fluid connector of the server is coupled to and in fluid communication with the manifold connector of the manifold.

Abstract: A method for forming a dielectric layer of a semiconductor is described. At first, providing a substrate with a metal-conductive layer having been formed thereon. Next covering the substrate with a membrane having a plurality of micro-holes. Afterward spraying a fluid dielectric on the membrane having a plurality of micro-holes. After waiting a period of time for the gaps among the metal conductors being filled with the fluid dielectric, removing the membrane having a plurality of micro-holes from the substrate. Further baking the substrate to cure the fluid dielectric inside metal-conductive layer. The thickness of the dielectric after curing is approximately equal to the thickness of the metal-conductive layer. At last forming a cap dielectric layer on the substrate.

Abstract: A process for making split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an interpoly dielectric layer.

Abstract: A MOS transistor with a pair of lightly doped drain (LDD) sub-regions in the substrate and whose gate electrode is self-aligned with a non-doped gate oxide layer overlying the channel region between the two LDD sub-regions.

Abstract: A method of manufacturing an electron tunnel oxide (ETOX) flash memory device having an improved coupling efficiency includes sequentially forming a tunnel oxide, a floating gate, a dielectric layer, and a control gate on a substrate, where the tunnel oxide and the bottom of the floating gate are formed to be narrower than the top of the floating gate, the dielectric and the control gate.

Abstract: A split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an inter-poly dielectric layer.

Abstract: A structure of dynamic random access memory includes a field effect transistor (FET), a capacitor, a world line and a bit line. The gate of the FET is electrically coupled to the word line in which a voltage source is supplied through the world line to the gate. The drain region of the FET is electrically coupled to a lower electrode of the capacitor. The capacitor has an upper electrode being electrically coupled to the gate of the FET either. The source region of the FET is electrically coupled to the bit line.