Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate, and forming a source/drain (S/D) structure over the fin structure. The method for forming a FinFET device structure also includes forming an inter-layer dielectric (ILD) structure covering the S/D structure, and forming a gate structure over the fin structure and adjacent to the S/D structure. The method for forming a FinFET device structure further includes forming a first hard mask layer over the gate structure, and forming a second hard mask layer over the first hard mask layer. In addition, the method for forming a FinFET device structure includes etching the ILD structure to form an opening exposing the S/D structure. The opening and a recess in the second hard mask layer are formed simultaneously.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure formed over the fin structure. The FinFET device structure also includes a contact formed over the fin structure and adjacent to the gate structure. The FinFET device structure further includes a first hard mask layer formed over the gate structure, and an upper portion of the first hard mask layer has an inverted-T shape. In addition, the FinFET device structure includes a second hard mask layer formed over the contact, and the second hard mask layer has a T shape.

Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate, and forming a source/drain (S/D) structure over the fin structure. The method for forming a FinFET device structure also includes forming an inter-layer dielectric (ILD) structure covering the S/D structure, and forming a gate structure over the fin structure and adjacent to the S/D structure. The method for forming a FinFET device structure further includes forming a first hard mask layer over the gate structure, and forming a second hard mask layer over the first hard mask layer. In addition, the method for forming a FinFET device structure includes etching the ILD structure to form an opening exposing the S/D structure. The opening and a recess in the second hard mask layer are formed simultaneously.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure formed over the fin structure. The FinFET device structure also includes a contact formed over the fin structure and adjacent to the gate structure. The FinFET device structure further includes a first hard mask layer formed over the gate structure, and an upper portion of the first hard mask layer has an inverted-T shape. In addition, the FinFET device structure includes a second hard mask layer formed over the contact, and the second hard mask layer has a T shape.

Abstract: A dummy cell pattern includes a dummy diffusion pattern disposed within a predetermined region A; a trench isolation pattern encompassing the dummy diffusion pattern in the predetermined region A; a first dummy gate pattern disposed on the dummy diffusion pattern with two ends of the first dummy gate pattern extending above the trench isolation pattern, thereby forming overlapping areas C1 and C2; and a second dummy gate pattern directly on the trench isolation pattern forming an overlapping area C therebetween, wherein the combination of C1, C2 and C is about 5%-20% of the predetermined region A.

Abstract: A dummy cell pattern includes a dummy diffusion pattern disposed within a predetermined region A; a trench isolation pattern encompassing the dummy diffusion pattern in the predetermined region A; a first dummy gate pattern disposed on the dummy diffusion pattern with two ends of the first dummy gate pattern extending above the trench isolation pattern, thereby forming overlapping areas C1 and C2; and a second dummy gate pattern directly on the trench isolation pattern forming an overlapping area C therebetween, wherein the combination of C1, C2 and C is about 5%-20% of the predetermined region A.

Abstract: A method of unifying device performance within an integrated circuit die includes providing a layout of an integrated circuit die with multiple functional circuit blocks; filling a field between the multiple functional circuit blocks with dummy diffusion patterns; and filling the field between the multiple functional circuit blocks with dummy gate patterns such that the dummy gate patterns and the dummy diffusion patterns are completely overlapped.

Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.

Abstract: A metal-insulator-metal capacitor structure includes a lower electrode, a buffer layer, a barrier layer, a dielectric layer and an upper electrode. The lower electrode is disposed in the buffer layer. The barrier layer covers part of the lower electrode and is disposed between the lower electrode and the upper electrode. The buffer layer serves as an etching stop layer to define the dielectric layer. The dielectric layer in the metal-insulator-metal capacitor structure has a uniform and ideal thickness.

Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Abstract: A metal-insulator-metal capacitor structure includes a lower electrode, a buffer layer, a barrier layer, a dielectric layer and an upper electrode. The lower electrode is disposed in the buffer layer. The barrier layer covers part of the lower electrode and is disposed between the lower electrode and the upper electrode. The buffer layer serves as an etching stop layer to define the dielectric layer. The dielectric layer in the metal-insulator-metal capacitor structure has a uniform and ideal thickness.

Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.

Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.