Patents by Inventor Yu-Hsiang CHAO
Yu-Hsiang CHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972951Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.Type: GrantFiled: April 4, 2022Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
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Publication number: 20230063687Abstract: An apparatus for polishing a wafer is provided. The apparatus includes a wafer carrier assembly including a head body and a retainer arrangement. The retainer arrangement includes a first retainer segment coupled to an underside of the head body and adjacent an outer sidewall of the wafer carrier and a second retainer segment, separate from the first retainer segment, coupled to the underside of the head body and adjacent the outer sidewall of the wafer carrier. Undersides of the first retainer segment and the second retainer segment are below an underside of the wafer carrier.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventor: Yu-Hsiang CHAO
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Patent number: 11521939Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a die and a stiffener. The substrate has an upper surface. The die is disposed on the upper surface of the substrate. The stiffener is disposed on the upper surface of the substrate and surrounds the die. The stiffener has a first upper surface adjacent to the die, a second upper surface far from the die and a lateral surface extending from the first upper surface to the second upper surface. A first distance between the first upper surface of the stiffener and the upper surface of the substrate is less than a second distance between the second upper surface of the stiffener and the upper surface of the substrate.Type: GrantFiled: July 24, 2020Date of Patent: December 6, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jui-Tzu Chen, Yu-Hsing Lin, Chia-Chieh Hu, Chun-Cheng Kuo, Yu-Hsiang Chao
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Publication number: 20220246483Abstract: In an embodiment, a system includes: a pad comprising a first side and a second side opposite the first side, wherein the first side is configured to receive a wafer during chemical mechanical planarization (CMP), and a platen adjacent the pad along the second side, wherein the platen comprises a suction opening that interfaces with the second side; a pump configured to produce suction at the suction opening to adhere the second side to the platen; and a sensor configured to collect sensor data characterizing a uniformity of adherence between the pad and the platen, wherein the pump is configured to produce the suction at the suction opening based on the sensor data.Type: ApplicationFiled: April 14, 2022Publication date: August 4, 2022Inventors: Yu-Hsiang CHAO, Chi-Ping Lei
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Patent number: 11328965Abstract: In an embodiment, a system includes: a pad comprising a first side and a second side opposite the first side, wherein the first side is configured to receive a wafer during chemical mechanical planarization (CMP), and a platen adjacent the pad along the second side, wherein the platen comprises a suction opening that interfaces with the second side; a pump configured to produce suction at the suction opening to adhere the second side to the platen; and a sensor configured to collect sensor data characterizing a uniformity of adherence between the pad and the platen, wherein the pump is configured to produce the suction at the suction opening based on the sensor data.Type: GrantFiled: July 22, 2019Date of Patent: May 10, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hsiang Chao, Chi-Ping Lei
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Publication number: 20220028800Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a die and a stiffener. The substrate has an upper surface. The die is disposed on the upper surface of the substrate. The stiffener is disposed on the upper surface of the substrate and surrounds the die. The stiffener has a first upper surface adjacent to the die, a second upper surface far from the die and a lateral surface extending from the first upper surface to the second upper surface. A first distance between the first upper surface of the stiffener and the upper surface of the substrate is less than a second distance between the second upper surface of the stiffener and the upper surface of the substrate.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jui-Tzu CHEN, Yu-Hsing LIN, Chia-Chieh HU, Chun-Cheng KUO, Yu-Hsiang CHAO
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Publication number: 20210136007Abstract: A method for orchestrating resources in a multi-access edge computing (MEC) network is applied in and by an apparatus. The MEC network comprises at least one control node, substrate nodes and substrate links managed by the at least one control node. The apparatus receives a virtual network request and calculates whether a proper virtual network embedding solution for the virtual network request exists. If so, the apparatus hands the solution over to the at least one control node for implementation.Type: ApplicationFiled: June 18, 2020Publication date: May 6, 2021Inventors: HUNG-YU WEI, CHUN-TING CHOU, KUO-LIANG CHANG CHIEN, YAO CHIANG, YU-HSIANG CHAO
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Patent number: 10986036Abstract: A method for orchestrating resources in a multi-access edge computing (MEC) network is applied in and by an apparatus. The MEC network comprises at least one control node, substrate nodes and substrate links managed by the at least one control node. The apparatus receives a virtual network request and calculates whether a proper virtual network embedding solution for the virtual network request exists. If so, the apparatus hands the solution over to the at least one control node for implementation.Type: GrantFiled: June 18, 2020Date of Patent: April 20, 2021Assignee: HON LIN TECHNOLOGY CO., LTD.Inventors: Hung-Yu Wei, Chun-Ting Chou, Kuo-Liang Chang Chien, Yao Chiang, Yu-Hsiang Chao
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Publication number: 20200043814Abstract: In an embodiment, a system includes: a pad comprising a first side and a second side opposite the first side, wherein the first side is configured to receive a wafer during chemical mechanical planarization (CMP), and a platen adjacent the pad along the second side, wherein the platen comprises a suction opening that interfaces with the second side; a pump configured to produce suction at the suction opening to adhere the second side to the platen; and a sensor configured to collect sensor data characterizing a uniformity of adherence between the pad and the platen, wherein the pump is configured to produce the suction at the suction opening based on the sensor data.Type: ApplicationFiled: July 22, 2019Publication date: February 6, 2020Inventors: Yu-Hsiang CHAO, Chi-Ping LEI
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Publication number: 20190247974Abstract: A method for performing a chemical mechanical polishing (CMP) is disclosed. The method includes supplying a slurry onto a polishing pad, holding a first wafer against the polishing pad by a first polishing head, holding a second wafer against the polishing pad by a second polishing head, and rotating the polishing pad.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Yi TSAI, Wen-Pin HO, Chieh-Han LEE, Yu-Hsiang CHAO
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Patent number: 10265829Abstract: A chemical mechanical polishing system includes a platen, a slurry introduction device and at least one polishing head. The platen is configured to allow a polishing pad to be disposed thereon. The slurry introduction device is configured to supply slurry onto the polishing pad. The polishing head includes a main body and at least one grinding piece. The main body has an accommodation space for accommodating a wafer. The grinding piece is disposed on the main body. The grinding piece has a grinding surface configured to grind against the polishing pad.Type: GrantFiled: October 30, 2015Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Yi Tsai, Wen-Pin Ho, Chieh-Han Lee, Yu-Hsiang Chao
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Patent number: 10256173Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first package body and at least one connecting element. The substrate has a first surface. The first package body is disposed adjacent to the first surface of the substrate, and defines at least one cavity. The connecting element is disposed adjacent to the first surface of the substrate and in a corresponding cavity. A space is defined between a periphery surface of a portion of the connecting element and a sidewall of a portion of the cavity. An end portion of the connecting element extends beyond an outermost surface of the first package body.Type: GrantFiled: February 22, 2016Date of Patent: April 9, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jun-Chieh Wu, Yu-Hsiang Chao, Chung-Yao Chang, Chun-Cheng Kuo
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Publication number: 20170243813Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first package body and at least one connecting element. The substrate has a first surface. The first package body is disposed adjacent to the first surface of the substrate, and defines at least one cavity. The connecting element is disposed adjacent to the first surface of the substrate and in a corresponding cavity. A space is defined between a periphery surface of a portion of the connecting element and a sidewall of a portion of the cavity. An end portion of the connecting element extends beyond an outermost surface of the first package body.Type: ApplicationFiled: February 22, 2016Publication date: August 24, 2017Inventors: Jun-Chieh WU, Yu-Hsiang CHAO, Chung-Yao CHANG, Chun-Cheng KUO
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Publication number: 20170120414Abstract: A chemical mechanical polishing system includes a platen, a slurry introduction device and at least one polishing head. The platen is configured to allow a polishing pad to be disposed thereon. The slurry introduction device is configured to supply slurry onto the polishing pad. The polishing head includes a main body and at least one grinding piece. The main body has an accommodation space for accommodating a wafer. The grinding piece is disposed on the main body. The grinding piece has a grinding surface configured to grind against the polishing pad.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Inventors: Yu-Yi TSAI, Wen-Pin HO, Chieh-Han LEE, Yu-Hsiang CHAO