Abstract: An electrical detection method provides a wiring structure including a base material body and a plurality of contact portions bonded to the base material body. Each of the contact portions includes an electrical detection pad exposed from a surface of the base material body, an electrical auxiliary pad exposed from the surface of the base material body, and a conductor that electrically connects the electrical detection pad and the electrical auxiliary pad. When probes of a detection device are connected to the contact portions, each of the probes exerts a force on the electrical detection pad and the electrical auxiliary pad of each of the contact portions at the same time, so that the contact force between the probes and the contact portions is enhanced to facilitate the electrical testing.

Abstract: A FinFET LDMOS device includes a semiconductor substrate; juxtaposed first well and second well in the semiconductor substrate; semiconductor fins extending on the semiconductor substrate along a first direction, the semiconductor fins including a first fin portion in the first well and a second fin portion in the second well; an extra semiconductor body adjoining the first fin portion and the second fin portion and extending along a second direction; a source region on the first fin portion; a drain region on the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, and the extra semiconductor body is covered by the gate; and a single-diffusion break structure embedded in the second fin portion and between the gate and drain region.

Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Abstract: A balance control device and system are provided. The balance control device includes a balance carrier, a force detector, a control device, and an posture detector. The balance carrier carries a user and presents a corresponding posture according to a force exerted on the balance carrier. The force detector is position in the balance carrier to detect the force to obtain a first sensing data. The posture detector is positioned in the control device and is configured to detect an posture of the control device to obtain a second sensing data. The control device obtains a first result according to the first sensing data and the second sensing data, and transmits the first result to a controlled device for controlling the controlled device to carry out a corresponding processing according to the first result.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

Abstract: A random number generator includes a pre-processing circuit and a chaos random number generator (CRNG). The pre-processing circuit includes a perturbation source and a control circuit, wherein the control circuit is coupled to the perturbation source. The CRNG, which is coupled to the pre-processing circuit, includes a chaos system and a post-processing circuit, wherein the post-processing circuit is coupled to the chaos system.

Abstract: An electrically-contactless joystick includes a housing, a handle, a first limiting member, a second limiting member, an elastic member, a magnet, and a magnetic sensor. The handle extends through the housing. The first limiting member and the second limiting member are fixed to the handle and movably clamped with the housing. The elastic member is connected to each of the first limiting member, the second limiting member, and the housing. The second limiting member abuts against the handle. The magnet is fixed to either the handle or the housing, and the magnetic sensor is fixed to the other. A terminal device is also provided.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a bottom package having a first sidewall and a second sidewall opposite to each other; a hybrid path layer disposed on the bottom package, wherein the hybrid path layer comprises an optical path layer and an electrical path layer, and at least one optical path of the optical path layer extends from the first sidewall of the bottom package beyond a center of the bottom package; and a plurality of dies bonded onto the hybrid path layer.

Abstract: A light-emitting device array includes a first light-emitting device, a second light-emitting device, and a third light-emitting device. A first beam shaping structure of the first light-emitting device is configured to convert light emitted by a first light-emitting structure of first light-emitting device into first structured light. A second beam shaping structure of the second light-emitting device is configured to convert light emitted by a second light-emitting structure of second light-emitting device into second structured light. Speckle patterns and spatial distributions of the first structured light and the second structured light on a projection plane are the same. A third beam shaping structure of the third light-emitting device is configured to convert light emitted by a third light-emitting structure of third light-emitting device into third structured light.

Abstract: A resistance-adjustable self-power-generating treadmill includes a chassis; a power generator; a belt driving device including two rollers, a circulating running belt, and a power transmission unit; a controller electrically connected with the power generator; a battery electrically connected with the controller; a handlebar; and display and control unit, which is mounted on the handlebar to allow a user to watch messages and to control, through touching the display and control unit, the controller to adjust the power generation amount of the power generator. Through adjusting the power generation amount of the power generator, the resisting force that is applied from the power generator to the circulating running belt is also controllable.

Abstract: A plating membrane includes a support structure extending radially outward from a nozzle that is to direct a flow of a plating solution toward a wafer. The plating membrane also includes a frame, supported by the support structure, having an inner wall that is angled outward from the nozzle. The outward angle of the inner wall relative to the nozzle directs a flow of plating solution from the nozzle in a manner that increases uniformity of the flow of the plating solution toward the wafer, reduces the amount of plating solution that is redirected inward toward the center of the plating membrane, reduces plating material voids in trenches of the wafer (e.g., high aspect ratio trenches), and/or the like.

Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Abstract: A redistribution structure is made using filler-free insulating materials with high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.