Patents by Inventor Yu-Hsiang Chen

Yu-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250079363
    Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface. A height of the step-height is smaller than a thickness of the first bonding layer.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Patent number: 12243839
    Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: March 4, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Patent number: 12236814
    Abstract: A display method and a display system for an anti-dizziness reference image are provided. The display system includes a display, a range extraction unit, an information analyzing unit, an object analyzing unit and an image setting unit. The display is used to display the anti-dizziness reference image. The range extraction unit is used to obtain a gaze background range of a user. The image setting unit is used to set an image hue, an image lightness, an image brightness, an image content or an ambient lighting display content of the anti-dizziness reference image according to a background hue information, a background lightness information, a background brightness information, or a road information of the gaze background range; or set an image ratio between the anti-dizziness reference image and a display area of the display according to an object distance or an object area of the watched object.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: February 25, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ya-Rou Hsu, Chien-Ju Lee, Hong-Ming Dai, Yu-Hsiang Tsai, Chia-Hsun Tu, Kuan-Ting Chen
  • Publication number: 20250059995
    Abstract: A multifunctional expansion bolt assembly includes a sleeve, a screw rod, and a connecting member. The sleeve includes a hollow body formed between first and second ends of the sleeve. The second end has at least one open groove. The screw rod includes a threaded portion. At least a portion of the threaded portion protrudes beyond the first end of the sleeve. A second end of the screw rod includes a conic portion having gradually increasing diameters towards the second end of the screw rod. The conic portion has a maximal diameter greater than an inner diameter of the second end of the sleeve. The screw rod includes at least one engaging portion having non-circular cross section and engaging with the at least one open groove. The connecting member includes an inner threading in threading connection with a portion of the threaded portion of the screw rod.
    Type: Application
    Filed: September 25, 2023
    Publication date: February 20, 2025
    Inventors: Yu-Hsiang Su, I-Chun Chen
  • Publication number: 20250054775
    Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 13, 2025
    Inventors: Ching-Yi Lin, Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen
  • Publication number: 20250056859
    Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Jia-He Lin, Yu-Ruei Chen, Yu-Hsiang Lin
  • Patent number: 12218082
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 12218009
    Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Che Tu, Wei-Chih Chen, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Publication number: 20250040213
    Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yi-Hsiang Chao, Peng-Hao Hsu, Yu-Shiuan Wang, Chi-Yuan Chen, Yu-Hsiang Liao, Chun-Hsien Huang, Hung-Chang Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 12211751
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20250028396
    Abstract: A method, system, apparatus, and/or device for detecting pinch gestures in an augmented reality environment. The method, system, apparatus, and/or device may include: a wearable display, a sensor, and a processing device. The wearable display may be configured to attach to a head of a user and display an augmented reality environment to the user. The sensor may be configured to detect a position of a first digit of a hand of the user and detect a position of a second digit of the hand of the user. The processing device may be configured to: identify a first fingertip of the first digit; identify a second fingertip of the second digit; determine that the first fingertip and the second fingertip are in an open pinch position at a first point in time; and display a cursor at a midpoint between the first fingertip and the second fingertip.
    Type: Application
    Filed: March 1, 2024
    Publication date: January 23, 2025
    Inventors: Yu-Hsiang Chen, Neeraj Kulkami
  • Patent number: 12207449
    Abstract: A cooling apparatus is provided. An external cooling fluid flows into an external inlet opening from an external inlet pipe and passes through a heat exchanger to flow out of an external outlet opening to an external outlet pipe. An internal cooling fluid flows into an internal inlet pipe from the server and flows into an internal inlet opening from the internal inlet pipe and passes through the heat exchanger for heat exchange with the external cooling fluid to flow out of an internal outlet opening to an internal outlet pipe. A hot-swap pump has a pump main body, an inlet anti-leakage pipe, an outlet anti-leakage pipe and a hot-swap connector. The inlet anti-leakage pipe includes an inlet connector and an inlet anti-leakage valve. The outlet anti-leakage pipe includes an outlet connector and an outlet anti-leakage valve. The hot-swap connector is electrically connected to the pump main body.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: January 21, 2025
    Assignee: Super Micro Computer, Inc.
    Inventors: Chia-Wei Chen, Te-Chang Lin, Yueh-Ming Liu, Yu-Hsiang Huang, Ya-Lin Liu, Chi-Che Chang
  • Publication number: 20250004562
    Abstract: A method, system, apparatus, and/or device that may include a sensor configured to obtain position information of at least a portion of a hand in a space relative to a first axis and a second axis. The method, system, apparatus, and/or device may include a processing device configured to: determine that fingers and a thumb of the hand are located within the defined area based on the position information; determine a first position of the fingers and a second position of the thumb based on the position information; in response to the fingers being in a clenched position, generate hand position information that only includes position information of the thumb; and in response to the position information of the thumb indicated the thumb is extended and oriented in a first direction along a first axis or a second axis, execute a first instruction.
    Type: Application
    Filed: February 14, 2024
    Publication date: January 2, 2025
    Inventors: Ganesh Salvi, Neeraj Kulkarni, Yu-Hsiang Chen
  • Patent number: 12165947
    Abstract: A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Sheh Huang, Yung-Shih Cheng, Jiing-Feng Yang, Yu-Hsiang Chen, Chii-Ping Chen
  • Publication number: 20240387365
    Abstract: a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Hsiang Chen, Wen-Sheh Huang, Po-Hsiang Huang, Hsiu-Wen Hsueh
  • Publication number: 20240371948
    Abstract: a transistor and an interconnect structure disposed over the transistor. The interconnect structure includes a first dielectric layer, a first conductive feature in the first dielectric layer, a first etch stop layer (ESL) disposed over the first dielectric layer and the first conductive feature, a dielectric feature disposed in the first ESL, an electrode disposed over the dielectric feature, and a second ESL disposed on the first ESL and the electrode.
    Type: Application
    Filed: July 10, 2024
    Publication date: November 7, 2024
    Inventors: Yu-Hsiang Chen, Po-Hsiang Huang, Wen-Sheh Huang, Hsing-Leo Tsai, Chia-En Huang
  • Publication number: 20240353931
    Abstract: A free space input standard is instantiated on a processor. Free space input is sensed and communicated to the processor. If the free space input satisfies the free space input standard, a touch screen input response is invoked in an operating system. The free space input may be sensed using continuous implicit, discrete implicit, active explicit, or passive explicit approaches. The touch screen input response may be invoked through communicating virtual touch screen input, a virtual input event, or a virtual command to or within the operating system. in this manner free space gestures may control existing touch screen interfaces and devices, without modifying those interfaces and devices directly to accept free space gestures.
    Type: Application
    Filed: December 1, 2023
    Publication date: October 24, 2024
    Inventors: Shashwat Kandadai, Nathan Abercrombie, Yu-Hsiang Chen, Sleiman Itani
  • Patent number: 12119262
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer and a first conductive feature and a second conductive feature surrounded by the first dielectric layer. The semiconductor device structure also includes a second dielectric layer over the first dielectric layer and a resistive element electrically connected to the first conductive feature. The second dielectric layer surrounds a portion of the resistive element. The semiconductor device structure further includes a conductive via electrically connected to the second conductive feature. The second dielectric layer surrounds a portion of the conductive via, and a contact area between the resistive element and the first conductive feature is wider than a contact area between the conductive via and the second conductive feature.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Sheh Huang, Hsiu-Wen Hsueh, Yu-Hsiang Chen, Chii-Ping Chen
  • Patent number: 12086326
    Abstract: A method, system, apparatus, and/or device for moving or scrolling a virtual object in a virtual or augmented reality environment. The method, system, apparatus, and/or device may include: detecting, by a first sensor, a first gesture associated with selecting a first virtual object in an augmented reality environment displayed by a head-mounted display; displaying, by the head-mounted display, a first indicator indicating a selection of the first virtual object by a user; detecting, using the first sensor or a second sensor, a first movement of the head-mounted display associated with a first movement command; and in response to detecting the first movement of the head-mounted display, executing the first movement command, where the first movement command is a scrolling function to scroll text or a graphical object of the first virtual object or a movement function to move the text or the graphical object of the first virtual object.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: September 10, 2024
    Assignee: West Texas Technology Partners, LLC
    Inventors: Yu-Hsiang Chen, Soulaiman Itani
  • Patent number: 12068377
    Abstract: a transistor and an interconnect structure disposed over the transistor. The interconnect structure includes a first dielectric layer, a first conductive feature in the first dielectric layer, a first etch stop layer (ESL) disposed over the first dielectric layer and the first conductive feature, a dielectric feature disposed in the first ESL, an electrode disposed over the dielectric feature, and a second ESL disposed on the first ESL and the electrode.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hsiang Chen, Po-Hsiang Huang, Wen-Sheh Huang, Hsing-Leo Tsai, Chia-En Huang