Patents by Inventor Yu-Hsiang Chen

Yu-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250004562
    Abstract: A method, system, apparatus, and/or device that may include a sensor configured to obtain position information of at least a portion of a hand in a space relative to a first axis and a second axis. The method, system, apparatus, and/or device may include a processing device configured to: determine that fingers and a thumb of the hand are located within the defined area based on the position information; determine a first position of the fingers and a second position of the thumb based on the position information; in response to the fingers being in a clenched position, generate hand position information that only includes position information of the thumb; and in response to the position information of the thumb indicated the thumb is extended and oriented in a first direction along a first axis or a second axis, execute a first instruction.
    Type: Application
    Filed: February 14, 2024
    Publication date: January 2, 2025
    Inventors: Ganesh Salvi, Neeraj Kulkarni, Yu-Hsiang Chen
  • Patent number: 12185497
    Abstract: A fluid immersion cooling system has a fluid tank containing a hydrocarbon dielectric fluid as a coolant fluid. One or more components of an electronic system is immersed in the coolant fluid. A gas cylinder contains a non-flammable, compressed filling gas. The temperature of the coolant fluid is monitored during operation of the electronic system. The filling gas is released from the gas cylinder and into the fluid tank when the temperature of the coolant fluid rises to a trigger temperature that is set based on the flash point of the coolant fluid. The filling gas covers a surface of the coolant fluid to block oxygen from interacting with vapors of the coolant fluid to prevent combustion.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: December 31, 2024
    Assignee: Super Micro Computer, Inc.
    Inventors: Yueh-Ming Liu, Hsiao-Chung Chen, Chia-Wei Chen, Yu-Hsiang Huang, Chia-Che Chang, Hua-Kai Tong, Tan-Hsin Chang, Yu-Chuan Chang, Ming-Yu Chen, Yu-Yen Hsiung, Kun-Chieh Liao
  • Publication number: 20240421249
    Abstract: A light-emitting device comprises a first semiconductor layer; a semiconductor mesa, comprising an active layer and a second semiconductor layer and comprising an inclined surface; a contact electrode covering the second semiconductor layer and comprising a first side surface; an insulating reflective structure covering the contact electrode and comprising a plurality of insulating reflective structure openings; a connection layer covering the insulating reflective structure and filling into the plurality of insulating reflective structure openings, and comprising a second side surface; and a metal reflective layer covering the connection layer and filling into the plurality of insulating reflective structure openings, and comprising a third side surface; wherein in a cross-sectional view of the light-emitting device, a first pitch is between the first side surface and the inclined surface, a third pitch is between the third side surface and the inclined surface, and the third pitch is smaller than the first
    Type: Application
    Filed: June 12, 2024
    Publication date: December 19, 2024
    Inventors: Meng-Hsiang HONG, Yu-Ling LIN, Chao-Hsing CHEN, Chen OU, Chien-Ya HUNG
  • Publication number: 20240411051
    Abstract: A light-emitting device array includes a first light-emitting device, a second light-emitting device, and a third light-emitting device. A first beam shaping structure of the first light-emitting device is configured to convert light emitted by a first light-emitting structure of first light-emitting device into first structured light. A second beam shaping structure of the second light-emitting device is configured to convert light emitted by a second light-emitting structure of second light-emitting device into second structured light. Speckle patterns and spatial distributions of the first structured light and the second structured light on a projection plane are the same. A third beam shaping structure of the third light-emitting device is configured to convert light emitted by a third light-emitting structure of third light-emitting device into third structured light.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 12, 2024
    Inventors: Jun-Da CHEN, Yu-Heng HONG, Wen-Cheng HSU, Tzu-Hsiang LAN, Hao-Chung KUO
  • Patent number: 12165947
    Abstract: A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Sheh Huang, Yung-Shih Cheng, Jiing-Feng Yang, Yu-Hsiang Chen, Chii-Ping Chen
  • Patent number: 12159791
    Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Yi Lin, Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen
  • Publication number: 20240391761
    Abstract: A method is provided that includes forming a first metal layer of a seal structure over a micro-electromechanical system (MEMS) structure and over a channel formed through the MEMS structure to an integrated circuit of a semiconductor structure. The first metal layer is formed at a first temperature. The method includes forming a second metal layer over the first metal layer. The second metal layer is formed at a second temperature less than the first temperature. The method includes performing a first cooling process to cool the semiconductor structure.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Kai-Lan CHANG, Yu-Lung YEH, Yen-Hsiu CHEN, Shuo Yen TAI, Yung-Hsiang CHEN
  • Publication number: 20240395909
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Publication number: 20240387265
    Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Pin-Wen Chen, Chang-Ting Chung, Yi-Hsiang Chao, Yu-Ting Wen, Kai-Chieh Yang, Yu-Chen Ko, Peng-Hao Hsu, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20240387365
    Abstract: a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Hsiang Chen, Wen-Sheh Huang, Po-Hsiang Huang, Hsiu-Wen Hsueh
  • Publication number: 20240387194
    Abstract: A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Chih Chen, Yu-Hsiang Hu, Hung-Jui Kuo, Sih-Hao Liao
  • Publication number: 20240387586
    Abstract: One or more semiconductor processing tools may deposit a contact etch stop layer on a substrate. In some implementations, the contact etch stop layer is comprised of less than approximately 12 percent hydrogen. Depositing the contact etch stop layer may include depositing contact etch stop layer material at a temperature of greater than approximately 600 degrees Celsius, at a pressure of greater than approximately 150 torr, and/or with a ratio of at least approximately 70:1 of NH3 and SiH4, among other examples. The one or more semiconductor processing tools may deposit a silicon-based layer above the contact etch stop layer. The one or more semiconductor processing tools may perform an etching operation into the silicon-based layer until reaching the contact etch stop layer to form a trench isolation structure.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Cheng-Hsien CHEN, Yung-Hsiang CHEN, Chia Hao LI, Yu-Lung YEH, Yen-Hsiu CHEN
  • Publication number: 20240386854
    Abstract: A cockpit display system includes a cockpit, a first display apparatus, a second display apparatus, a first light sensor, a second light sensor and a brightness distribution calculation module. The first light sensor is suitable for detecting a first ambient light brightness. The second light sensor is suitable for detecting a second ambient light brightness. The brightness distribution calculation module is suitable for respectively calculating a first brightness, a second brightness, a third brightness and a fourth brightness of the first display area and the second display area of the first display apparatus and the third display area and the fourth display area of the second display apparatus under a same display gray level according to the first ambient light brightness and the second ambient light brightness. The first brightness, the second brightness, the third brightness and the fourth brightness are different from each other.
    Type: Application
    Filed: December 21, 2023
    Publication date: November 21, 2024
    Inventors: Yu-Chi CHEN, Teng-Ying HUANG, Chih-Hsiang LIU, Li-Heng HSU, Chi-Yu LIU, Tsung-Hsiung WANG, Chia-Sheng CHENG
  • Patent number: 12147811
    Abstract: A warp scheduling method includes: storing multiple first warps issued to a streaming multiprocessor in an instruction buffer module; marking multiple second warps which are able to be scheduled in the first warps by a schedulable warp indication window, wherein the number of the marked second warps is the size of the schedulable warp indication window; sampling a load/store unit stall cycle in each time interval to obtain a load/store unit stall cycle proportion; comparing the load/store unit stall cycle proportion with a stall cycle threshold value, and adjusting the size of the schedulable warp indication window and determining the second warps according to the comparison result; and issuing the second warps from the instruction buffer module to a processing module for execution.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 19, 2024
    Inventors: Chung-ho Chen, Chien-ming Chiu, Yu-hsiang Wang
  • Publication number: 20240379451
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20240379606
    Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Shih-Peng Tai, Yu-Hsiang Hu, I-Chia Chen
  • Publication number: 20240379584
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Publication number: 20240379444
    Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
    Type: Application
    Filed: July 14, 2024
    Publication date: November 14, 2024
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
  • Publication number: 20240379075
    Abstract: An anti-dizziness display method, a processing device, and an information display system are proposed. The information display system is configured to display on a mobile vehicle and includes a first display, a transportation environment information acquisition device, and a processing device. The transportation environment information acquisition device is configured to obtain transportation environment information of the mobile vehicle. The processing device is configured to perform the following operations. A visual feedback magnitude is determined according to the transportation environment information, and the visual feedback magnitude varies in response to variation of the transportation environment information. A display image of the first display is controlled according to the visual feedback magnitude, so that the display image of the first display changes in response to the variation in the transportation environment information.
    Type: Application
    Filed: March 6, 2024
    Publication date: November 14, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Hong-Ming Dai, Ya-Rou Hsu, Chien-Ju Lee, Chun-Yen Huang, Kuan-Ting Chen, Yu-Hsiang Tsai, Chia-Hsun Tu
  • Publication number: 20240371873
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first active region, forming an interlayer dielectric layer over a source/drain region of the first active region, forming a gate stack to surround the channel region of the first active region, and etching the gate stack and the interlayer dielectric layer to form a cutting trench. The cutting trench includes a first portion extending into the gate stack and a second portion extending into the interlayer dielectric layer. A first width of the first portion of the cutting trench is different than a second width of the second portion of the cutting trench in a direction parallel to a longitudinal axis of the gate stack. The method also includes forming a gate cutting structure in the cutting trench.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Chih CHEN, Fu-Hsiang SU, Yu-San CHIEN, Shih-Hsun CHANG