Patents by Inventor Yu-Hsiang Huang

Yu-Hsiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12283514
    Abstract: The present disclosure provides a method and a system therefore for processing wafer. The method includes: extracting a first gas from a chamber via a first route; blocking a second route used to be pumped down to chuck a wafer placed in the chamber, wherein the second route connects the chamber and the first route; and providing a second gas via a third route to purge a junction of the first route and the second route.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-Chun Yang, Chih-Lung Cheng, Yi-Ming Lin, Po-Chih Huang, Yu-Hsiang Juan, Xuan-Yang Zheng, Ren-Jyue Wang, Chih-Yuan Wang
  • Publication number: 20250123807
    Abstract: A random number generator includes a pre-processing circuit and a chaos random number generator (CRNG). The pre-processing circuit includes a perturbation source and a control circuit, wherein the control circuit is coupled to the perturbation source. The CRNG, which is coupled to the pre-processing circuit, includes a chaos system and a post-processing circuit, wherein the post-processing circuit is coupled to the chaos system.
    Type: Application
    Filed: July 2, 2024
    Publication date: April 17, 2025
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Cheng-Bin Chen, Tsung Chen, Yuan-Hao Huang, Yu-Hsiang Huang
  • Publication number: 20250126781
    Abstract: A semiconductor device includes a non-volatile memory structure. A layout of metallization layers in the semiconductor device coupled with the non-volatile memory structure is configured to achieve a low likelihood of electromigration in the non-volatile memory structure, particularly at operating temperature parameters associated with demanding applications such as automotive and/or industrial, among other examples. The non-volatile memory structure is electrically coupled with a first metallization layer. The first metallization layer electrically couples the non-volatile memory structure with a second metallization layer that is configured as a write bit line metallization layer for the non-volatile memory structure. The first metallization layer electrically couples the non-volatile memory structure with a third metallization layer above the second metallization layer. The third metallization layer is configured as a read bit line metallization layer for the non-volatile memory structure.
    Type: Application
    Filed: February 1, 2024
    Publication date: April 17, 2025
    Inventors: Chen-Ming HUANG, Shih-Hsien CHEN, Yu-Hsiang YANG
  • Patent number: 12277423
    Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: April 15, 2025
    Assignee: SIGMASTAR TECHNOLOGY LTD.
    Inventors: Cheng-Chi Huang, Shu-Cheng Chou, Yu-Hsiang Lin
  • Patent number: 12277977
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Grant
    Filed: May 13, 2024
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Patent number: 12272600
    Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Wen Chen, Chang-Ting Chung, Yi-Hsiang Chao, Yu-Ting Wen, Kai-Chieh Yang, Yu-Chen Ko, Peng-Hao Hsu, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 12255638
    Abstract: The disclosure provides an electrical apparatus, including a substrate, a plurality of gate driver units and a plurality of gate lines. The gate driver units are disposed on the substrate. The gate lines are disposed on the substrate. Each of the gate lines is respectively electrically connected to the corresponding gate driver unit. Each of the gate lines is configured to transmit a respective gate signal. The gate lines include a first gate line and a second gate line. The first gate line and the second gate line are configured to transmit the respective gate signals at a same time.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: March 18, 2025
    Assignee: Innolux Corporation
    Inventors: Hsiu-Yi Tsai, Yu-Ti Huang, Yu-Hsiang Chiu, Yi-Hung Lin
  • Publication number: 20250085548
    Abstract: A light field display module including a light field display layer, an adjustment layer, and an image forming layer is provided. The light field display layer is configured to form a light field image beam. The adjustment layer is disposed on a path of the light field image beam, and configured to adjust the light field image beam. The image forming layer is disposed on the path of the light field image beam from the adjustment layer, and configured to change a position of a light field image by changing a direction of the light field image beam. The image forming layer has multiple optical micro-structures.
    Type: Application
    Filed: August 1, 2024
    Publication date: March 13, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Szu-Wei Wu, Yi-Hsiang Huang, Chia-Ping Lin, Yu-Hsiang Liu, Hung Tsou
  • Patent number: 12249024
    Abstract: Examples of the disclosure describe systems and methods for presenting virtual content on a wearable head device. In some embodiments, a state of a wearable head device is determined by minimizing a total error based on a reduced weight associated with a reprojection error. A view reflecting the determined state of the wearable head device is presented via a display of the wearable head device. In some embodiments, a wearable head device calculates a preintegration term based on the image data received via a sensor of the wearable head device and the inertial data received via a first IMU and a second IMU of the wearable head device. The wearable head device estimates a position of the device based on the preintegration term, and the wearable head device presents the virtual content based on the position of the device.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: March 11, 2025
    Assignee: Magic Leap, Inc.
    Inventors: Yu-Hsiang Huang, Evan Gregory Levine, Igor Napolskikh, Dominik Michael Kasper, Manel Quim Sanchez Nicuesa, Sergiu Sima, Benjamin Langmann, Ashwin Swaminathan, Martin Georg Zahnert, Blazej Marek Czuprynski, Joao Antonio Pereira Faro, Christoph Tobler, Omid Ghasemalizadeh
  • Publication number: 20250067271
    Abstract: A ventilation system comprises a ventilation fan with a lamp for installing to a ceiling having an installation opening. The ventilation fan comprises a housing, a fan module, a power box, a junction box, a lamp module and a support. The housing has a first opening and an air outlet. The fan module comprises an inlet opening and an outlet opening. The outlet opening communicates with the air outlet. The power box has a first circuit board. The lamp module and the housing are located at opposite sides of the installation opening. The junction box is electrically connected to the first circuit board and the lamp module. The impeller comprises a hub, and a ratio of a height of the hub to a height of the housing is less than 0.5. A ratio of a height of the impeller to a height of the housing is greater than 0.65.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: YU-HSIANG HUANG, YUAN-CHUAN LIU, CHIH-HUA LIN
  • Publication number: 20250056746
    Abstract: An electronic device including a device housing, a cable, a cable positioning structure, and a housing restriction structure is provided. The device housing includes a through hole. The through hole includes a central region, a first channel region, and a second channel region. The cable passes through the device housing. The cable positioning structure is disposed on the cable. The cable positioning structure includes a first protrusion and a second protrusion. The cable positioning structure is adapted to be rotated between a first orientation and a second orientation relative to the device housing. The housing restriction structure is disposed on the device housing. The housing restriction structure includes a first restrain member and a first stopper. In a positioned state, the cable positioning structure is in the second orientation. The first restrain member and the first stopper restrict the cable positioning structure.
    Type: Application
    Filed: July 18, 2024
    Publication date: February 13, 2025
    Inventors: Che-Cheng WU, Chen-Wei HUANG, Yu-Hsiang LIN, Ya-Hui LO
  • Publication number: 20250056823
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20250054775
    Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 13, 2025
    Inventors: Ching-Yi Lin, Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen
  • Publication number: 20250040213
    Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yi-Hsiang Chao, Peng-Hao Hsu, Yu-Shiuan Wang, Chi-Yuan Chen, Yu-Hsiang Liao, Chun-Hsien Huang, Hung-Chang Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 12207449
    Abstract: A cooling apparatus is provided. An external cooling fluid flows into an external inlet opening from an external inlet pipe and passes through a heat exchanger to flow out of an external outlet opening to an external outlet pipe. An internal cooling fluid flows into an internal inlet pipe from the server and flows into an internal inlet opening from the internal inlet pipe and passes through the heat exchanger for heat exchange with the external cooling fluid to flow out of an internal outlet opening to an internal outlet pipe. A hot-swap pump has a pump main body, an inlet anti-leakage pipe, an outlet anti-leakage pipe and a hot-swap connector. The inlet anti-leakage pipe includes an inlet connector and an inlet anti-leakage valve. The outlet anti-leakage pipe includes an outlet connector and an outlet anti-leakage valve. The hot-swap connector is electrically connected to the pump main body.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: January 21, 2025
    Assignee: Super Micro Computer, Inc.
    Inventors: Chia-Wei Chen, Te-Chang Lin, Yueh-Ming Liu, Yu-Hsiang Huang, Ya-Lin Liu, Chi-Che Chang
  • Patent number: 12185497
    Abstract: A fluid immersion cooling system has a fluid tank containing a hydrocarbon dielectric fluid as a coolant fluid. One or more components of an electronic system is immersed in the coolant fluid. A gas cylinder contains a non-flammable, compressed filling gas. The temperature of the coolant fluid is monitored during operation of the electronic system. The filling gas is released from the gas cylinder and into the fluid tank when the temperature of the coolant fluid rises to a trigger temperature that is set based on the flash point of the coolant fluid. The filling gas covers a surface of the coolant fluid to block oxygen from interacting with vapors of the coolant fluid to prevent combustion.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: December 31, 2024
    Assignee: Super Micro Computer, Inc.
    Inventors: Yueh-Ming Liu, Hsiao-Chung Chen, Chia-Wei Chen, Yu-Hsiang Huang, Chia-Che Chang, Hua-Kai Tong, Tan-Hsin Chang, Yu-Chuan Chang, Ming-Yu Chen, Yu-Yen Hsiung, Kun-Chieh Liao
  • Publication number: 20240314976
    Abstract: A fluid immersion cooling system includes a fluid tank that contains a layer of a dual-phase coolant fluid and one or more layers of single-phase coolant fluids. The dual-phase and single-phase coolant fluids are immiscible, with the dual-phase coolant fluid having a lower boiling point and higher density than a single-phase coolant fluid. A substrate of an electronic system is submerged in the tank such that high heat-generating components are immersed at least in the layer of the dual-phase coolant fluid. Heat from the components is dissipated to the dual-phase coolant fluid to generate vapor bubbles of the dual-phase coolant fluid. The vapor bubbles rise to a layer of a single-phase coolant fluid that is above the layer of the dual-phase coolant fluid. The vapor bubbles condense to droplets of the dual-phase coolant fluid. The droplets fall down into the layer of the dual-phase coolant fluid.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 19, 2024
    Inventors: Yueh Ming LIU, Yu Hsiang HUANG, Yu Chuan CHANG, Tan Hsin CHANG, Hsiao Chung CHEN, Chia-Wei CHEN, Chih-Ta CHEN, Cheng-Hung LIN, Ming-Te HSU
  • Patent number: 12039093
    Abstract: An encrypted hard disk device is provided, including a near-field communication (NFC) sensing module, a processor, a storage unit, and a power switch. The NFC sensing module is configured to read a user identification (UID) of at least one sensor element. The processor is electrically connected to the NFC sensing module and the storage unit. The processor receives the UID and generates a control signal when the UID is approved. The power switch is electrically connected to the processor and the storage unit and maintains a conducting state according to the control signal and supplies power to the storage unit for accessing the storage unit.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: July 16, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Cheng-Yu Wang, Shao-Kai Liu, Yu-Hsiang Huang, Bo-Hua Yang
  • Patent number: 12029012
    Abstract: A fluid immersion cooling system includes a fluid tank that contains a layer of a dual-phase coolant fluid and one or more layers of single-phase coolant fluids. The dual-phase and single-phase coolant fluids are immiscible, with the dual-phase coolant fluid having a lower boiling point and higher density than a single-phase coolant fluid. A substrate of an electronic system is submerged in the tank such that high heat-generating components are immersed at least in the layer of the dual-phase coolant fluid. Heat from the components is dissipated to the dual-phase coolant fluid to generate vapor bubbles of the dual-phase coolant fluid. The vapor bubbles rise to a layer of a single-phase coolant fluid that is above the layer of the dual-phase coolant fluid. The vapor bubbles condense to droplets of the dual-phase coolant fluid. The droplets fall down into the layer of the dual-phase coolant fluid.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: July 2, 2024
    Assignee: Super Micro Computer, Inc.
    Inventors: Yueh Ming Liu, Yu Hsiang Huang, Yu Chuan Chang, Tan Hsin Chang, Hsiao Chung Chen, Chia-Wei Chen, Chih-Ta Chen, Cheng-Hung Lin, Ming-Te Hsu
  • Patent number: D1068055
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 25, 2025
    Assignee: Delta Electronics, Inc.
    Inventors: Ko-Neng Huang, Yu-Hsiang Huang, Yen-Lin Chen