Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: Provided are conductive structures located within dielectric material, and methods for fabricating such structures and devices. An exemplary method includes providing a substrate having a conductive feature in a first dielectric layer; depositing a second dielectric layer over the conductive feature and the first dielectric layer; etching the second dielectric layer to form a cavity through the second dielectric layer, wherein the cavity has a bottom with a convex profile; depositing a barrier layer along the bottom of the cavity; and depositing a conductive material in the cavity to form a structure electrically connected to the conductive feature.

Abstract: Examples of the disclosure describe systems and methods for presenting virtual content on a wearable head device. In some embodiments, a state of a wearable head device is determined by minimizing a total error based on a reduced weight associated with a reprojection error. A view reflecting the determined state of the wearable head device is presented via a display of the wearable head device. In some embodiments, a wearable head device calculates a preintegration term based on the image data received via a sensor of the wearable head device and the inertial data received via a first IMU and a second IMU of the wearable head device. The wearable head device estimates a position of the device based on the preintegration term, and the wearable head device presents the virtual content based on the position of the device.

Abstract: A wafer transporting method includes following operations. A plurality of wafers are received in a semiconductor container attached to a mobile vehicle. An air processing system is coupled to a wall of the semiconductor container. The air processing system includes an inlet valve, an outlet valve, a pump between the inlet valve and the outlet valve, and a desiccant coupled to the pump. The semiconductor container is moved. The pump of the air processing system is turned on to extract air from inside the semiconductor container into the air processing system through the inlet valve. Humidity of the air is reduced when the air passes through the desiccant of the air processing system. The air is returned back to the semiconductor container through the outlet valve.

Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.

Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a second dielectric layer on the high resistance layer, a low-k dielectric layer over the second dielectric layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: A ventilation fan includes a housing having an opening, a grille structure positioned to cover the opening, a fan module provided in the housing and a function module. The grille structure includes a base defining an outlet, and a grille support spaced apart from the base and connected by the connecting columns A radial inlet is formed between the base and the grille support is in communication with the outlet. The base includes a holder having a holding opening axially downward and faced away from the housing. The function module is disposed within the holder through the holding opening.

Abstract: A fluid immersion cooling system has a fluid tank containing a hydrocarbon dielectric fluid as a coolant fluid. One or more components of an electronic system is immersed in the coolant fluid. A gas cylinder contains a non-flammable, compressed filling gas. The temperature of the coolant fluid is monitored during operation of the electronic system. The filling gas is released from the gas cylinder and into the fluid tank when the temperature of the coolant fluid rises to a trigger temperature that is set based on the flash point of the coolant fluid. The filling gas covers a surface of the coolant fluid to block oxygen from interacting with vapors of the coolant fluid to prevent combustion.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for calibrating an augmented reality device using camera and inertial measurement unit data. In some implementations, a bundle adjustment process jointly optimizes or estimates states of the augmented reality device. The process can use, as input, visual and inertial measurements as well as factory-calibrated sensor extrinsic parameters. The process performs bundle adjustment and uses non-linear optimization of estimated states constrained by the measurements and the factory calibrated extrinsic parameters. The process can jointly optimize inertial constraints, IMU calibration, and camera calibrations. Output of the process can include most likely estimated states, such as data for a 3D map of an environment, a trajectory of the device, and/or updated extrinsic parameters of the visual and inertial sensors (e.g., cameras and IMUs).

Abstract: An organic-inorganic hybrid material is disclosure. The organic-inorganic hybrid material contains 5˜50 wt % of inorganic compounds and has a characteristic peak at 1050±50 cm?1 in FTIR spectrum. Furthermore, the invention also provides a fabricating process of the organic-inorganic hybrid material as well as its starting material “isocyanates”. In particular, the isocyanates are prepared from carbonate containing compounds and amines.

Abstract: A method for an image processing circuit includes steps of: receiving a fingerprint image; performing a low-pass filtering on the fingerprint image to remove a moiré signal on the fingerprint image, to generate a filtered image; and performing a data binning on the filtered image to generate an output image.

Abstract: A cooling apparatus is provided. An external cooling fluid flows into an external inlet opening from an external inlet pipe and passes through a heat exchanger to flow out of an external outlet opening to an external outlet pipe. An internal cooling fluid flows into an internal inlet pipe from the server and flows into an internal inlet opening from the internal inlet pipe and passes through the heat exchanger for heat exchange with the external cooling fluid to flow out of an internal outlet opening to an internal outlet pipe. A hot-swap pump has a pump main body, an inlet anti-leakage pipe, an outlet anti-leakage pipe and a hot-swap connector. The inlet anti-leakage pipe includes an inlet connector and an inlet anti-leakage valve. The outlet anti-leakage pipe includes an outlet connector and an outlet anti-leakage valve. The hot-swap connector is electrically connected to the pump main body.

Abstract: A server computer system has one or more node assemblies. A node assembly has two motherboards that are stacked one over another with their component sides facing toward each other. Memory cards that are mounted on one motherboard are interlaced with memory cards that are mounted on the other motherboard. At least processors of the two motherboards are immersed in a coolant fluid in a fluid immersion cooling tank. A processor cooling stack is mounted over a processor. The processor cooling stack includes flow regulation structures with sidewalls that regulate flow of vapor bubbles of the coolant fluid away from the processor.