Patents by Inventor Yu-Hsiang Hung

Yu-Hsiang Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991442
    Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
  • Patent number: 10978398
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Grant
    Filed: January 1, 2020
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 10978457
    Abstract: The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 13, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Yu-Hsiang Hung, Ming-Te Wei
  • Patent number: 10930517
    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 23, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen
  • Patent number: 10839516
    Abstract: A simulate segmentation method of cylinder and pie cake digital models utilizes a three-dimensional model and a reference point to cope with various shapes of the nuclear reactor structures. The segmentation simulation of the nuclear reactor structure is conducted with genetic algorithm. The segmentation simulation of the nuclear reactor structure is achieved by using the genetic algorithm to perform a double selection mechanism on the cross-sectional area of the nuclear reactor structure to select the optimal configuration of the segmentation, thus minimizing the cross-sectional areas of the nuclear reactor structure. The cutter segments the nuclear reactor structure based on the optimal configuration of the segmentation, thereby achieving the purpose of minimizing the attrition rate of a cutter and segmenting the nuclear reactor structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 17, 2020
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN
    Inventors: Yu-Hsiang Hung, Chung-Hao Huang, Shiang-Fong Chen, Po-Chou Tsai
  • Patent number: 10795255
    Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 6, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wei-Lun Hsu, Gang-Yi Lin, Yu-Hsiang Hung, Ying-Chih Lin, Feng-Yi Chang, Ming-Te Wei, Shih-Fang Tzou, Fu-Che Lee, Chia-Liang Liao
  • Patent number: 10786903
    Abstract: The present disclosure illustrates a map creation system and a method for a movable robot. The map creation system includes a movable robot and a display device. The movable robot includes a robot body; a driving unit driving the robot body to move in a space; an image capturing unit capturing a image in the space; a sampling unit sampling in the space to obtain a sample; a control unit controlling the operation of the driving unit, the image capturing unit and the sampling unit; and a power supply unit supplying an electrical power to each unit. The display device displays the received image and marks a location in the space where the sample is obtained on the image, and synchronously displays a movement trace of the movable robot in the space according to the driving instructions of the driving unit.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: September 29, 2020
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan
    Inventors: Chung-Hao Huang, Yu-Hsiang Hung, Chiung-Wei Huang, Cheng-Yuan Chang
  • Publication number: 20200135647
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Application
    Filed: January 1, 2020
    Publication date: April 30, 2020
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Publication number: 20200111795
    Abstract: The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 9, 2020
    Inventors: Li-Wei Feng, Yu-Hsiang Hung, Ming-Te Wei
  • Publication number: 20200111871
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 9, 2020
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Publication number: 20200105764
    Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 2, 2020
    Inventors: Wei-Lun Hsu, Gang-Yi Lin, Yu-Hsiang Hung, Ying-Chih Lin, Feng-Yi Chang, Ming-Te Wei, Shih-Fang Tzou, Fu-Che Lee, Chia-Liang Liao
  • Patent number: 10566285
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: February 18, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Publication number: 20200051248
    Abstract: A simulate segmentation method of cylinder and pie cake digital models utilizes a three-dimensional model and a reference point to cope with various shapes of the nuclear reactor structures. The segmentation simulation of the nuclear reactor structure is conducted with genetic algorithm. The segmentation simulation of the nuclear reactor structure is achieved by using the genetic algorithm to perform a double selection mechanism on the cross-sectional area of the nuclear reactor structure to select the optimal configuration of the segmentation, thus minimizing the cross-sectional areas of the nuclear reactor structure. The cutter segments the nuclear reactor structure based on the optimal configuration of the segmentation, thereby achieving the purpose of minimizing the attrition rate of a cutter and segmenting the nuclear reactor structure.
    Type: Application
    Filed: March 15, 2019
    Publication date: February 13, 2020
    Inventors: YU-HSIANG HUNG, CHUNG-HAO HUANG, SHIANG-FONG CHEN, PO-CHOU TSAI
  • Publication number: 20200035782
    Abstract: The present invention provides a semiconductor structure including a substrate including a plurality of capacitor lower electrodes, the capacitor lower electrodes are arranged in a diamond array along a first direction and a second direction respectively, the first direction and the second direction are not perpendicular to each other. A supporting structure layer contacts at least parts of the capacitor lower electrodes, wherein the supporting structure layer includes a plurality of triangular openings, and the three corners of each triangular opening are overlapped with three adjacent capacitor lower electrodes respectively.
    Type: Application
    Filed: August 29, 2018
    Publication date: January 30, 2020
    Inventors: Li-Wei Feng, En-Chiuan Liou, Yu-Cheng Tung, Wei-Lun Hsu, Yu-Hsiang Hung, Ming-Te Wei, Le-Tien Jung
  • Patent number: 10546922
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: January 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
  • Patent number: 10541304
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: January 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Patent number: 10529856
    Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: January 7, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Man-Ling Lu, Yu-Hsiang Hung, Chung-Fu Chang, Yen-Liang Wu, Wen-Jiun Shen, Chia-Jong Liu, Ssu-I Fu, Yi-Wei Chen
  • Patent number: 10497810
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first spacer adjacent to the first fin-shaped structure and a second spacer adjacent to the second fin-shaped structure; and using the first spacer and the second spacer as mask to remove part of the substrate for forming a third fin-shaped structure on the first region and a fourth fin-shaped structure on the second region, in which the third fin-shaped structure includes a first top portion and a first bottom portion and the fourth fin-shaped structure includes a second top portion and a second bottom portion.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: December 3, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Chih-Kai Hsu, Yu-Hsiang Hung, Jyh-Shyang Jenq
  • Publication number: 20190362981
    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.
    Type: Application
    Filed: August 6, 2019
    Publication date: November 28, 2019
    Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen
  • Patent number: 10418251
    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 17, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen