Abstract: Improved control of via anchor profiles in metals at a contact layer can be achieved by slowing down an anchor etching process and by introducing a passivation operation. By first passivating a metallic surface, etchants can be prevented from dispersing along grain boundaries, thereby distorting the shape of the via anchor. An iterative scheme that involves multiple cycles of alternating passivation and etching operations can control the formation of optimal via anchor profiles. When a desirable anchor shape is achieved, the anchor maintains structural integrity of the vias, thereby improving reliability of the interconnect structure.

Abstract: A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided.

Abstract: A method is described. The method includes obtaining a relationship between a thickness of a contamination layer formed on a mask and an amount of compensation energy to remove the contamination layer, obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device, and applying first compensation energy calculated from the relationship to a light directed to the mask.

Abstract: A method of detecting and identifying postures and gestures of a human user generates a reference model from a reference image and obtains an image of action or gesture being performed. The image is of a user and his flexible and hand-held portable device, and the image comprises a second identification feature. A state of a second feature of the second identification feature in the reference model can generate posture identification. The state of the second feature comprises size, shape, and location of the second identification feature in the hands of the user. A portable device and a non-volatile storage medium of a computer are also disclosed.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a ring-shaped supporting layer disposed on the sensor chip, and a light-permeable sheet that is disposed on the ring-shaped supporting layer. The light-permeable sheet has an outer surface and an inner surface that is opposite to the outer surface, and has a ring-shaped distribution groove that is opposite to the outer surface and that surrounds the inner surface. A top portion of the ring-shaped supporting layer is arranged in the ring-shaped distribution groove and abuts against a ring-shaped slanting wall of the ring-shaped distribution groove, so that a height of an inner supporting wall of the ring-shaped distribution groove is within a range from 120% to 150% of a height of an outer supporting wall of the ring-shaped distribution groove.

Abstract: A package includes a die, an encapsulant, and a redistribution structure. The encapsulant laterally encapsulates the die. The redistribution structure includes a first portion directly above the encapsulant and a second portion directly above the die. A thickness of the first portion of the redistribution structure decreases continuously from an edge of the package toward an interior of the package.

Abstract: A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.

Abstract: A method, system, apparatus, and/or device for moving or scrolling a virtual object in a virtual or augmented reality environment. The method, system, apparatus, and/or device may include: detecting, by a first sensor, a first gesture associated with selecting a first virtual object in an augmented reality environment displayed by a head-mounted display; displaying, by the head-mounted display, a first indicator indicating a selection of the first virtual object by a user; detecting, using the first sensor or a second sensor, a first movement of the head-mounted display associated with a first movement command; and in response to detecting the first movement of the head-mounted display, executing the first movement command, where the first movement command is a scrolling function to scroll text or a graphical object of the first virtual object or a movement function to move the text or the graphical object of the first virtual object.

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a plurality of read command sequences configured to instruct a rewritable non-volatile memory module to read a first physical unit by using a plurality of read voltage levels; after the read command sequences are sent, receiving first data from the rewritable non-volatile memory module, where the first data includes replacement data corresponding to a plurality of first bits reflecting a read result of a first memory cell by using the read voltage levels, and a data amount of the first data is less than a total data amount of the first bits; after the first data is received, performing data restoration on the first data to obtain a plurality of second bits; performing a decoding operation according to the second bits.

Abstract: The present disclosure relates to methods of processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The chemical vapor deposition chamber includes a spindle mechanism that cooperates with one or more carrier ring forks to move the semiconductor substrate from one station to another station. The methods include monitoring one or more spindle operation parameters and carrying out one or more maintenance steps on the spindle mechanism based on the results of monitoring the one or more spindle operation parameters. The monitored spindle operation parameters provide an indication of undesirable vibration of the semiconductor substrates in the processing chamber. The vibration of the semiconductor substrates in the processing chamber is undesirable because it promotes generation of unwanted particles that deposit onto a surface of the semiconductor substrate.

Abstract: A static random access memory (SRAM) includes a first active region and a second active region parallel to each other, a first gate structure crossing the first active region and the second active region, a first lower contact and a second lower contact respectively on the first active region and the second active region at a first side of the first gate structure, a third lower contact and a fourth lower contact respectively on the first active region and the second active region at a second side of the first gate structure. An edge of the first lower contact is aligned to an edge of the third lower contact while the other edges are not aligned. An edge of the second lower contact is aligned to an edge of the fourth lower contact while the other edges are not aligned.

Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first insulating layer, and a conductive pillar over the substrate. The conductive pillar is embedded in the first insulating layer, and a top surface of the conductive pillar is exposed by the first insulating layer. The method includes forming a second insulating layer over the first insulating layer and the conductive pillar. The second insulating layer has a hole over the top surface of the conductive pillar. The method includes forming a conductive via structure in the hole and a conductive line over the conductive via structure and the second insulating layer. The conductive via structure has a first strip shape in a first top view of the conductive via structure.

Abstract: An EUV lithography mask including a substrate, a patterned absorber layer including an alloy of rhodium. In some embodiments, the alloy of rhodium includes a group 5, group 6, group 9, group 10, or group 11 transition metal having a specific EUV refractive index and a specific EUV extinction coefficient. The disclosed EUV lithography masks reduce undesirable mask 3D effects.

Abstract: An interconnect structure according to the present disclosure includes a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.

Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

Abstract: A decoding method, comprising: sending a first read command sequence corresponding to a host system to read a first physical unit of a physical unit group to obtain a first data frame; responding to a decoding failure of a first single-frame decoding performed on the first data frame, sending a plurality of second read command sequences to read a plurality of second physical units in the physical unit group to obtain a plurality of second data frames; respectively performing a second single-frame decoding on the second data frames; performing a XOR operation on the corresponding data frame of each physical unit of the physical unit group to obtain first error evaluation information; generating enhanced first error evaluation information based on the first error evaluation information; and performing a third single-frame decoding on the first data frame based on the enhanced first error evaluation information.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A package structure and a method for forming a package structure are provided. The package structure includes a chip-containing structure bonded to a redistribution structure through multiple first solder bumps. The package structure also includes a memory-containing structure bonded to an interposer chip. The interposer chip is bonded to the redistribution structure through multiple second solder bumps. The package structure further includes a substrate, and the redistribution structure is over the substrate.

Abstract: An embodiment semiconductor package structure may include a first redistribution layer and a first semiconductor die attached to the first redistribution layer. The first semiconductor die may include first front-side electrical contacts and first back-side electrical contacts such that the first front-side electrical contacts are electrically connected to the first redistribution layer. The semiconductor package structure may further include a second redistribution layer formed over the first semiconductor die such that the second redistribution layer is electrically connected to the first back-side electrical contacts of the first semiconductor die and to a second semiconductor die attached to the second redistribution layer and positioned vertically over the first semiconductor die. The first semiconductor die may include at least two alignment marks separated by at least 50 microns.