Patents by Inventor Yu-Hsiang KAO
Yu-Hsiang KAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942652Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.Type: GrantFiled: April 13, 2022Date of Patent: March 26, 2024Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Chen-Ting Kao, Chi-Cheng Wen, Yu-Sheng Chang, Chih-Cheng Lee, Chiung-Hsiang Wu, Sheng-Li Yen, Yu-Cheng Zhang, Chang-Ju Hsieh, Chen Chao
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Patent number: 11865518Abstract: The instant disclosure provides a method for manufacturing an electroless plating substrate and a method for forming a metal layer on a surface of a substrate. The method for preparing the electroless plating substrate includes: providing a substrate; attaching a self-adsorbed catalyst composition to a surface of the substrate; and performing an electroless metal deposition for forming an electroless metal layer on the surface of the substrate. The self-adsorbed catalyst composition includes a colloidal nanoparticle and a silane compound. The colloidal nanoparticle includes a palladium nanoparticle and a capping agent enclosing the palladium nanoparticle. The silane compound has at least one amino group to interact with the colloidal nanoparticle. A covalent bond between the silane compound and the surface of the substrate is formed through the at least one silane group of the silane compound. The colloid nanoparticle has a particle size ranging from 5 to 10 nanometers.Type: GrantFiled: October 20, 2020Date of Patent: January 9, 2024Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Tzu-Chien Wei, Yu-Hsiang Kao
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Publication number: 20210046455Abstract: The instant disclosure provides a method for manufacturing an electroless plating substrate and a method for forming a metal layer on a surface of a substrate. The method for preparing the electroless plating substrate includes: providing a substrate; attaching a self-adsorbed catalyst composition to a surface of the substrate; and performing an electroless metal deposition for forming an electroless metal layer on the surface of the substrate. The self-adsorbed catalyst composition includes a colloidal nanoparticle and a silane compound. The colloidal nanoparticle includes a palladium nanoparticle and a capping agent enclosing the palladium nanoparticle. The silane compound has at least one amino group to interact with the colloidal nanoparticle. A covalent bond between the silane compound and the surface of the substrate is formed through the at least one silane group of the silane compound. The colloid nanoparticle has a particle size ranging from 5 to 10 nanometers.Type: ApplicationFiled: October 20, 2020Publication date: February 18, 2021Inventors: TZU-CHIEN WEI, YU-HSIANG KAO
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Patent number: 10828624Abstract: The instant disclosure provides a self-adsorbed catalyst composition, a method for preparing the self-adsorbed catalyst composition and a method for manufacturing an electroless plating substrate. The self-adsorbed catalyst composition includes colloidal nanoparticles and a silane compound. The colloidal nanoparticles include palladium nanoparticles and capping agents enclosing the palladium nanoparticles. The silane compound has at least an amino group, and an interaction is established between the amino group of the silane compound and the colloidal nanoparticle.Type: GrantFiled: September 18, 2018Date of Patent: November 10, 2020Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Tzu-Chien Wei, Yu-Hsiang Kao
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Publication number: 20190118165Abstract: The instant disclosure provides a self-adsorbed catalyst composition, a method for preparing the self-adsorbed catalyst composition and a method for manufacturing an electroless plating substrate. The self-adsorbed catalyst composition includes colloidal nanoparticles and a silane compound. The colloidal nanoparticles include palladium nanoparticles and capping agents enclosing the palladium nanoparticles. The silane compound has at least an amino group, and an interaction is established between the amino group of the silane compound and the colloidal nanoparticle.Type: ApplicationFiled: September 18, 2018Publication date: April 25, 2019Inventors: Tzu-Chien WEI, Yu-Hsiang KAO
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Patent number: 9754073Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.Type: GrantFiled: August 15, 2016Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Patent number: 9553043Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.Type: GrantFiled: April 3, 2012Date of Patent: January 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lee-Chung Lu, Wen-Hao Chen, Yuan-Te Hou, Fang-Yu Fan, Yu-Hsiang Kao, Dian-Hau Chen, Shyue-Shyh Lin, Chii-Ping Chen
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Publication number: 20160350473Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.Type: ApplicationFiled: August 15, 2016Publication date: December 1, 2016Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Patent number: 9418196Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.Type: GrantFiled: January 16, 2015Date of Patent: August 16, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Patent number: 9292645Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.Type: GrantFiled: November 24, 2014Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Publication number: 20150199469Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.Type: ApplicationFiled: January 16, 2015Publication date: July 16, 2015Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Publication number: 20150082259Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.Type: ApplicationFiled: November 24, 2014Publication date: March 19, 2015Inventors: HUANG-YU CHEN, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Patent number: 8898600Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.Type: GrantFiled: July 15, 2013Date of Patent: November 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Publication number: 20140282306Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.Type: ApplicationFiled: July 15, 2013Publication date: September 18, 2014Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Publication number: 20130256902Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.Type: ApplicationFiled: April 3, 2012Publication date: October 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lee-Chung LU, Wen-Hao CHEN, Yuan-Te HOU, Fang-Yu FAN, Yu-Hsiang KAO, Dian-Hau CHEN, Shyue-Shyh LIN, Chii-Ping CHEN